Device Modeling and Circuit Design of Neuromorphic Memory Structures

The downscaling of CMOS technology and the benefits gleaned thereof have made it the cornerstone of the semiconductor industry for many years. As the technology reaches its fundamental physical limits, however, CMOS is expected to run out of steam instigating the exploration of new nanoelectronic devices. Memristors have emerged as promising candidates for future computing paradigms, specifically, memory arrays and neuromorphic circuits. Towards this end, this dissertation will explore the use of two memristive devices, namely, Transition Metal Oxide (TMO) devices and Insulator Metal Transition (IMT) devices in constructing neuromorphic circuits. A compact model for TMO devices is first proposed and verified against experimental data. The proposed model, unlike most of the other models present in the literature, leverages the instantaneous resistance of the device as the state variable which facilitates parameter extraction. In addition, a model for the forming voltage of TMO devices is developed and verified against experimental data and Monte Carlo simulations. Impact of the device geometry and material characteristics of the TMO device on the forming voltage is investigated and techniques for reducing the forming voltage are proposed. The use of TMOs in syanptic arrays is then explored and a multi-driver write scheme is proposed that improves their performance. The proposed technique enhances voltage delivery across the selected cells via suppressing the effective line resistance and leakage current paths, thus, improving the performance of the crossbar array. An IMT compact model is also developed and verified against experiemntal data and electro-thermal device simulations. The proposed model describes the device as a memristive system with the temperature being the state variable, thus, capturing the temperature dependent resistive switching of the IMT device in a compact form suitable for SPICE implementation. An IMT based Integrate-And-Fire neuron is then proposed. The IMT neuron leverages the temperature dynamics of the device to deliver the functionality of the neuron. The proposed IMT neuron is more compact than its CMOS counterparts as it alleviates the need for complex CMOS circuitry. Impact of the IMT device parameters on the neuron\u27s performance is then studied and design considerations are provided

Formal Approaches to Control System Security From Static Analysis to Runtime Enforcement

With the advent of Industry 4.0, industrial facilities and critical infrastructures are transforming into an ecosystem of heterogeneous physical and cyber components, such as programmable logic controllers, increasingly interconnected and therefore exposed to cyber-physical attacks, i.e., security breaches in cyberspace that may adversely affect the physical processes underlying industrial control systems. The main contributions of this thesis follow two research strands that address the security concerns of industrial control systems via formal methodologies. As our first contribution, we propose a formal approach based on model checking and statistical model checking, within the MODEST TOOLSET, to analyse the impact of attacks targeting nontrivial control systems equipped with an intrusion detection system (IDS) capable of detecting and mitigating attacks. Our goal is to evaluate the impact of cyber-physical attacks, i.e., attacks targeting sensors and/or actuators of the system with potential consequences on the safety of the inner physical process. Our security analysis estimates both the physical impact of the attacks and the performance of the IDS. As our second contribution, we propose a formal approach based on runtime enforcement to ensure specification compliance in networks of controllers, possibly compromised by colluding malware that may tamper with actuator commands, sensor readings, and inter-controller communications. Our approach relies on an ad-hoc sub-class of Ligatti et al.’s edit automata to enforce controllers represented in Hennessy and Regan’s Timed Process Language. We define a synthesis algorithm that, given an alphabet P of observable actions and a timed correctness property e, returns a monitor that enforces the property e during the execution of any (potentially corrupted) controller with alphabet P, and complying with the property e. Our monitors correct and suppress incorrect actions coming from corrupted controllers and emit actions in full autonomy when the controller under scrutiny is not able to do so in a correct manner. Besides classical requirements, such as transparency and soundness, the proposed enforcement enjoys deadlock- and diverge-freedom of monitored controllers, together with compositionality when dealing with networks of controllers. Finally, we test the proposed enforcement mechanism on a non-trivial case study, taken from the context of industrial water treatment systems, in which the controllers are injected with different malware with different malicious goals

Modeling of reverse current effects in trench-based smart power technologies

The increase in complexity in todays automotive products is driven by the trend to implement new features in the area of safety, comfort and entertainment. This significantly raises the safety requirements of new ICs and the identification of possible sources of failures gains in priority. One of these failure sources is the injection of parasitic currents into the common substrate of a chip. This does not only occur during exceptions in the operation of the IC but also affects applications which require switching of inductive loads. The difficulty to handle substrate current injection originates from its nonlocality as it potentially influences the entire IC. In this thesis a point-to-point modeling scheme for Spice-based circuit simulation is proposed. It addresses parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. These models represent the three main components in the coupling path which are the forward biased diode at the perturbing device, the reverse biased diode at the susceptible node, and the intermediary common substrate of the chip. An automated layout extraction framework identifies the injectors of the minority carriers and the sensitive devices. Additionally, it determines the relevant parameters for the models. The curve fitting functions of the models are derived from calibrated TCAD simulations which are based on the measurement results of two dedicated test chips. The test chips were specifically designed to provide detailed analysis capabilities of this parasitic coupling effect. This led to a design which contains several different injector nodes and a large number of susceptible nodes spread over the entire area of the chip. Additionally, the chip incorporates the most commonly used layout-based guard structures to obtain an in-depth insight on their efficiency in recent BCD technologies. Based on the results obtained by measurements of the test chips the underlying physics of the coupling effect are discussed in detail. Minority carrier injection in the substrate is not much different to the operating principle of a bipolar transistor and the differences and similarities between them are presented. This forms the basis of the model development and explains how the equations of the Verilog-AMS models were derived. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip

Bio-inspired learning and hardware acceleration with emerging memories

Machine Learning has permeated many aspects of engineering, ranging from the Internet of Things (IoT) applications to big data analytics. While computing resources available to implement these algorithms have become more powerful, both in terms of the complexity of problems that can be solved and the overall computing speed, the huge energy costs involved remains a significant challenge. The human brain, which has evolved over millions of years, is widely accepted as the most efficient control and cognitive processing platform. Neuro-biological studies have established that information processing in the human brain relies on impulse like signals emitted by neurons called action potentials. Motivated by these facts, the Spiking Neural Networks (SNNs), which are a bio-plausible version of neural networks have been proposed as an alternative computing paradigm where the timing of spikes generated by artificial neurons is central to its learning and inference capabilities. This dissertation demonstrates the computational power of the SNNs using conventional CMOS and emerging nanoscale hardware platforms. The first half of this dissertation presents an SNN architecture which is trained using a supervised spike-based learning algorithm for the handwritten digit classification problem. This network achieves an accuracy of 98.17% on the MNIST test data-set, with about 4X fewer parameters compared to the state-of-the-art neural networks achieving over 99% accuracy. In addition, a scheme for parallelizing and speeding up the SNN simulation on a GPU platform is presented. The second half of this dissertation presents an optimal hardware design for accelerating SNN inference and training with SRAM (Static Random Access Memory) and nanoscale non-volatile memory (NVM) crossbar arrays. Three prominent NVM devices are studied for realizing hardware accelerators for SNNs: Phase Change Memory (PCM), Spin Transfer Torque RAM (STT-RAM) and Resistive RAM (RRAM). The analysis shows that a spike-based inference engine with crossbar arrays of STT-RAM bit-cells is 2X and 5X more efficient compared to PCM and RRAM memories, respectively. Furthermore, the STT-RAM design has nearly 6X higher throughput per unit Watt per unit area than that of an equivalent SRAM-based (Static Random Access Memory) design. A hardware accelerator with on-chip learning on an STT-RAM memory array is also designed, requiring $16$ bits of floating-point synaptic weight precision to reach the baseline SNN algorithmic performance on the MNIST dataset. The complete design with STT-RAM crossbar array achieves nearly 20X higher throughput per unit Watt per unit mm^2 than an equivalent design with SRAM memory. In summary, this work demonstrates the potential of spike-based neuromorphic computing algorithms and its efficient realization in hardware based on conventional CMOS as well as emerging technologies. The schemes presented here can be further extended to design spike-based systems that can be ubiquitously deployed for energy and memory constrained edge computing applications

Embedded System Design

A unique feature of this open access textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This fourth edition has been updated and revised to reflect new trends and technologies, such as the importance of cyber-physical systems (CPS) and the Internet of things (IoT), the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues

Embedded System Design

A unique feature of this open access textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This fourth edition has been updated and revised to reflect new trends and technologies, such as the importance of cyber-physical systems (CPS) and the Internet of things (IoT), the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues

Modulation and Multiple Access Techniques for Ultra-Wideband Communication Systems

Two new energy detection (ED) Ultra-Wideband (UWB) systems are proposed in this dissertation. The first one is an ED UWB system based on pulse width modulation (PWM). The bit error rate (BER) performance of this ED PWM system is slightly worse than ED pulse position modulation (PPM) system in additive white Gaussian noise (AWGN) channels. However, the BER performance of this ED PWM system surpasses that of a PPM system in multipath channels since a PWM system does not suffer cross-modulation interference (CMI) as a PPM system. In the presence of synchronization errors, the BER performance of a PWM system also surpasses that of a PPM system. The second proposed ED UWB system is based on using two pulses, which are the different-order derivatives of the Gaussian pulse, to transmitted bit 0 or 1. These pulses are appropriately chosen to separate their spectra in frequency domain.The receiver is composed of two energy detection branches and each branch has a filter which captures the signal energy of either bit 0 or 1. The outputs of two branches are subtracted from each other to generate the decision statistic and the value of this statistic is compared to a threshold to determine the transmitted bits. This system is named as acf{GFSK} system in this dissertation and it exhibits the same BER performance as a PPM system in AWGN channels. In multipath channels, a GFSK system surpasses a PPM system because it does not suffer CMI. And the BER performance of a GFSK system is better than a PPM system in the presence of synchronization errors. When a GFSK system is compared to a PWM system, it will always achieve approximately 2 dB improvement in AWGN channels, multipath channels, and in the presence synchronization errors. However, a PWM system uses lower-order derivatives of the Gaussian pulse to transmit signal, and this leads to a simple pulse generator. In this dissertation, an optimal threshold is applied to improve PPM system performance. The research results show that the application of an optimal threshold can e

Modulation and Multiple Access Techniques for Ultra-Wideband Communication Systems

Two new energy detection (ED) Ultra-Wideband (UWB) systems are proposed in this dissertation. The first one is an ED UWB system based on pulse width modulation (PWM). The bit error rate (BER) performance of this ED PWM system is slightly worse than ED pulse position modulation (PPM) system in additive white Gaussian noise (AWGN) channels. However, the BER performance of this ED PWM system surpasses that of a PPM system in multipath channels since a PWM system does not suffer cross-modulation interference (CMI) as a PPM system. In the presence of synchronization errors, the BER performance of a PWM system also surpasses that of a PPM system. The second proposed ED UWB system is based on using two pulses, which are the different-order derivatives of the Gaussian pulse, to transmitted bit 0 or 1. These pulses are appropriately chosen to separate their spectra in frequency domain.The receiver is composed of two energy detection branches and each branch has a filter which captures the signal energy of either bit 0 or 1. The outputs of two branches are subtracted from each other to generate the decision statistic and the value of this statistic is compared to a threshold to determine the transmitted bits. This system is named as acf{GFSK} system in this dissertation and it exhibits the same BER performance as a PPM system in AWGN channels. In multipath channels, a GFSK system surpasses a PPM system because it does not suffer CMI. And the BER performance of a GFSK system is better than a PPM system in the presence of synchronization errors. When a GFSK system is compared to a PWM system, it will always achieve approximately 2 dB improvement in AWGN channels, multipath channels, and in the presence synchronization errors. However, a PWM system uses lower-order derivatives of the Gaussian pulse to transmit signal, and this leads to a simple pulse generator. In this dissertation, an optimal threshold is applied to improve PPM system performance. The research results show that the application of an optimal threshold can e

Real-Time Trigger and online Data Reduction based on Machine Learning Methods for Particle Detector Technology

Moderne Teilchenbeschleuniger-Experimente generieren während zur Laufzeit immense Datenmengen. Die gesamte erzeugte Datenmenge abzuspeichern, überschreitet hierbei schnell das verfügbare Budget für die Infrastruktur zur Datenauslese. Dieses Problem wird üblicherweise durch eine Kombination von Trigger- und Datenreduktionsmechanismen adressiert. Beide Mechanismen werden dabei so nahe wie möglich an den Detektoren platziert um die gewünschte Reduktion der ausgehenden Datenraten so frühzeitig wie möglich zu ermöglichen. In solchen Systeme traditionell genutzte Verfahren haben währenddessen ihre Mühe damit eine effiziente Reduktion in modernen Experimenten zu erzielen. Die Gründe dafür liegen zum Teil in den komplexen Verteilungen der auftretenden Untergrund Ereignissen. Diese Situation wird bei der Entwicklung der Detektorauslese durch die vorab unbekannten Eigenschaften des Beschleunigers und Detektors während des Betriebs unter hoher Luminosität verstärkt. Aus diesem Grund wird eine robuste und flexible algorithmische Alternative benötigt, welche von Verfahren aus dem maschinellen Lernen bereitgestellt werden kann. Da solche Trigger- und Datenreduktion-Systeme unter erschwerten Bedingungen wie engem Latenz-Budget, einer großen Anzahl zu nutzender Verbindungen zur Datenübertragung und allgemeinen Echtzeitanforderungen betrieben werden müssen, werden oft FPGAs als technologische Basis für die Umsetzung genutzt. Innerhalb dieser Arbeit wurden mehrere Ansätze auf Basis von FPGAs entwickelt und umgesetzt, welche die vorherrschenden Problemstellungen für das Belle II Experiment adressieren. Diese Ansätze werden über diese Arbeit hinweg vorgestellt und diskutiert werden