De-RISC: A complete RISC-V based space-grade platform

The H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and basic multicore space-grade processors in the market; (2) access to an increasingly rich software ecosystem rather than sticking to the slowly fading SPARC and PowerPC-based ones; (3) freedom (or drastic reduction) of export and license restrictions imposed by commercial ISAs such as Arm; and (4) improved support for the design and validation of safety-related real-time applications, (5) being the platform with software qualified and hardware designed per established space industry standards. De-RISC partners have set up the different layers of the platform during the first phases of the project. However, they have recently boosted integration and assessment activities. This paper introduces the De-RISC space platform, presents recent progress such as enabling virtualization and software qualification, new MPSoC features, and use case deployment and evaluation, including a comparison against other commercial platforms. Finally, this paper introduces the ongoing activities that will lead to the hardware and fully qualified software platform at TRL8 on FPGA by September 2022.This project has received funding from the European Union’s Horizon 2020 Research and Innovation programme under Grant Agreement EIC-FTI 869945. BSC work has also been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-07255GBC21/AEI/10.13039/501100011033.Peer ReviewedPostprint (author's final draft

Operating System Kernels on Multi-core Architectures

Operating System (OS) kernels have been under research and development for decades, mainly assuming single processor and distributed hardware systems. With the recent rise of multi-core chips that may incorporate a network on chip (NoC), new challenges have appeared that were not considered before. Given that a complete multi-core system that works on a single system on chip (SoC) is now the normal case, different cores on a single SoC may share other physical resources and data. This new sharing scheme on a SoC affects crucial aspects of an overall system like correctness, performance, predictability, scalability and security. Both hardware and OSs to flexibly cooperate in order to provide solutions for such challenges. SoC mimics the internet somehow now, with different cores acting as computer nodes, and the network medium is given in an advanced digital fabrics like buses or NoCs, that are a current research area. However, OSs are still assuming some (hardware) features like single physical memory and memory sharing for inter-process communication, page-based protection, cache operations, even when evolving from uniprocessor to multi-core processors. Such features not only may degrade performance and other system aspects, but also some of them make no sense for a multi-core SoC, and introduce some barriers and limitations. While new OS research is considering different kernel designs to cope up with multi-core systems, they are still limited by the current commercial hardware architectures. The objective of this thesis is to assess different kernel designs and implementations on multi-core hardware architectures. Part of the contributions of the thesis is porting RTEMS (RTOS) and seL4 microkernel to Epiphany and RISC-V hardware architectures respectively, trading-off the design and implementation decisions. This hands-on experience gave a better understanding of the real-world challenges regarding kernel designs and implementations

MBBench: WCET Kıyaslama Kümesi

One of the important features of any real-time software is the worst-case execution time (WCET). To get an understanding of the timing behavior of real-time systems and to prove that the real-time software meets its deadlines, WCET analysis is performed. Today, researchers actively develop new WCET analysis methods and tools. Therefore, they need benchmark programs to evaluate and compare their work. To meet this need, in this study we present a new benchmark suite, called MBBench. MBBench includes a collection of C programs for Linux operating system and RTEMS real-time operating system. Its main aim is to help the evaluation and comparison of measurement-based WCET analysis methods/tools. MBBench has been published as open source. It can be obtained freely over the Internet.Herhangi bir gerçek zamanlı yazılımın en önemli özelliklerinden birisi, en kötü durum yürütme süresidir (WCET)._x000D_ Gerçek zamanlı sistemlerin zamanlama davranışını anlamak ve gerçek zamanlı yazılımın son teslim tarihlerini_x000D_ karşıladığını kanıtlamak için WCET analizi yapılır. Günümüzde araştırmacılar aktif olarak yeni WCET analiz_x000D_ yöntemleri ve araçları geliştirmektedir. Dolayısıyla, çalışmalarını değerlendirmek ve karşılaştırmak için kıyaslama_x000D_ programlarına ihtiyaç duymaktadırlar. Bu çalışmada, bu ihtiyacı karşılamaya yardımcı olmak amacıyla MBBench_x000D_ isminde yeni bir kıyaslama kümesi sunuyoruz. MBBench, Linux işletim sistemi ve RTEMS gerçek zamanlı işletim_x000D_ sistemi için C programları koleksiyonu içermektedir. Kıyaslama kümesinin temel amacı, ölçüm tabanlı WCET_x000D_ analizi yöntemlerinin/araçlarının değerlendirilmesine ve karşılaştırılmasına yardımcı olmaktır. MBBench, açık_x000D_ kaynak kodlu olarak yayınlanmıştır ve İnternet üzerinden ücretsiz olarak edinilebilir.Herhangi bir gerçek zamanlı yazılımın en önemli özelliklerinden birisi, en kötü durum yürütme süresidir (WCET). Gerçek zamanlı sistemlerin zamanlama davranışını anlamak ve gerçek zamanlı yazılımın son teslim tarihlerini karşıladığını kanıtlamak için WCET analizi yapılır. Günümüzde araştırmacılar aktif olarak yeni WCET analiz yöntemleri ve araçları geliştirmektedir. Dolayısıyla, çalışmalarını değerlendirmek ve karşılaştırmak için kıyaslama programlarına ihtiyaç duymaktadırlar. Bu çalışmada, bu ihtiyacı karşılamaya yardımcı olmak amacıyla MBBench isminde yeni bir kıyaslama kümesi sunuyoruz. MBBench, Linux işletim sistemi ve RTEMS gerçek zamanlı işletim sistemi için C programları koleksiyonu içermektedir. Kıyaslama kümesinin temel amacı, ölçüm tabanlı WCET analizi yöntemlerinin/araçlarının değerlendirilmesine ve karşılaştırılmasına yardımcı olmaktır. MBBench, açık kaynak kodlu olarak yayınlanmıştır ve İnternet üzerinden ücretsiz olarak edinilebilir

A Survey of Operating Systems Infrastructure for Embedded Systems

Since early applications in the 1960s, embedded systems have come down in price and there has been a dramatic rise in processing power and functionality. In addition, embedded systems are becoming increasingly complex. High-end devices, such as mobile phones, PDAs, entertainment devices, and set-top boxes, feature millions of lines of code with varying degrees of assurance of correctness. Nowadays, more and more embedded systems are implemented in a distributed way, a wide range of high-performance distributed embedded systems have been designed and deployed. As a lot of aspects of embedded system design become increasingly dependent on the effective interaction of distributed processors, it is clear that as much effort needs to be focused on software infrastructure, such as operating systems, with respect to how to provide functionality in order to fulfill these requirements. This technical report presents some of the approaches associated to operating systems that have been used in order to fulfill these needs.CAPES/MEC - Brasil, Project BEX3342/08-

Partitioned System with XtratuM on PowerPC

XtratuM is a real-time hypervisor originally built on x86 architecture. It is designed referencing the concept of partitioned system. The main work in this thesis is to implement XtratuM in PowerPC architecture.Zhou, R. (2009). Partitioned System with XtratuM on PowerPC. http://hdl.handle.net/10251/12738Archivo delegad

Applying Hypervisor-Based Fault Tolerance Techniques to Safety-Critical Embedded Systems

This document details the work conducted through the development of this thesis, and it is structured as follows: • Chapter 1, Introduction, has briefly presented the motivation, objectives, and contributions of this thesis. • Chapter 2, Fundamentals, exposes a series of concepts that are necessary to correctly understand the information presented in the rest of the thesis, such as the concepts of virtualization, hypervisors, or software-based fault tolerance. In addition, this chapter includes an exhaustive review and comparison between the different hypervisors used in scientific studies dealing with safety-critical systems, and a brief review of some works that try to improve fault tolerance in the hypervisor itself, an area of research that is outside the scope of this work, but that complements the mechanism presented and could be established as a line of future work. • Chapter 3, Problem Statement and Related Work, explains the main reasons why the concept of Hypervisor-Based Fault Tolerance was born and reviews the main articles and research papers on the subject. This review includes both papers related to safety-critical embedded systems (such as the research carried out in this thesis) and papers related to cloud servers and cluster computing that, although not directly applicable to embedded systems, may raise useful concepts that make our solution more complete or allow us to establish future lines of work. • Chapter 4, Proposed Solution, begins with a brief comparison of the work presented in Chapter 3 to establish the requirements that our solution must meet in order to be as complete and innovative as possible. It then sets out the architecture of the proposed solution and explains in detail the two main elements of the solution: the Voter and the Health Monitoring partition. • Chapter 5, Prototype, explains in detail the prototyping of the proposed solution, including the choice of the hypervisor, the processing board, and the critical functionality to be redundant. With respect to the voter, it includes prototypes for both the software version (the voter is implemented in a virtual machine) and the hardware version (the voter is implemented as IP cores on the FPGA). • Chapter 6, Evaluation, includes the evaluation of the prototype developed in Chapter 5. As a preliminary step and given that there is no evidence in this regard, an exercise is carried out to measure the overhead involved in using the XtratuM hypervisor versus not using it. Subsequently, qualitative tests are carried out to check that Health Monitoring is working as expected and a fault injection campaign is carried out to check the error detection and correction rate of our solution. Finally, a comparison is made between the performance of the hardware and software versions of Voter. • Chapter 7, Conclusions and Future Work, is dedicated to collect the conclusions obtained and the contributions made during the research (in the form of articles in journals, conferences and contributions to projects and proposals in the industry). In addition, it establishes some lines of future work that could complete and extend the research carried out during this doctoral thesis.Programa de Doctorado en Ciencia y Tecnología Informática por la Universidad Carlos III de MadridPresidente: Katzalin Olcoz Herrero.- Secretario: Félix García Carballeira.- Vocal: Santiago Rodríguez de la Fuent

NASA's Core Flight Software - A Reusable Real-Time Framework

No abstract availabl

Overlay virtualized wireless sensor networks for application in industrial internet of things : a review

Abstract: In recent times, Wireless Sensor Networks (WSNs) are broadly applied in the Industrial Internet of Things (IIoT) in order to enhance the productivity and efficiency of existing and prospective manufacturing industries. In particular, an area of interest that concerns the use of WSNs in IIoT is the concept of sensor network virtualization and overlay networks. Both network virtualization and overlay networks are considered contemporary because they provide the capacity to create services and applications at the edge of existing virtual networks without changing the underlying infrastructure. This capability makes both network virtualization and overlay network services highly beneficial, particularly for the dynamic needs of IIoT based applications such as in smart industry applications, smart city, and smart home applications. Consequently, the study of both WSN virtualization and overlay networks has become highly patronized in the literature, leading to the growth and maturity of the research area. In line with this growth, this paper provides a review of the development made thus far concerning virtualized sensor networks, with emphasis on the application of overlay networks in IIoT. Principally, the process of virtualization in WSN is discussed along with its importance in IIoT applications. Different challenges in WSN are also presented along with possible solutions given by the use of virtualized WSNs. Further details are also presented concerning the use of overlay networks as the next step to supporting virtualization in shared sensor networks. Our discussion closes with an exposition of the existing challenges in the use of virtualized WSN for IIoT applications. In general, because overlay networks will be contributory to the future development and advancement of smart industrial and smart city applications, this review may be considered by researchers as a reference point for those particularly interested in the study of this growing field