Drop Test and Finite Element Analysis of Test Board

AbstractMost electronic components have high precision and expensive features and people used the drop test to determine the reliability of these electronic components effectively. This study focused on the drop test of FR-4 test board according to the JEDEC standard, to understand the test board's basic mechanical properties and variations of stress and strain on test board. This study used finite element analysis software ANSYS/LS-DYNA to perform a drop test simulation of test board under JESD22-B111 standard, with 0.5ms pulse duration time and 1500G peak acceleration as test conditions. The support excitation method was used to predict the test board response during impact. The results between full model and quarter model were compared to verify the accuracy and efficiency of finite element analysis

Characterization of electronic board material properties under impact loaDing

On-board electronics in advanced military equipment are often subjected to severe ballistic shocks and vibrations. Impact and shock to such products can cause significant functional and physical damage. Safeguarding on-board electronic sensors from such transient shocks due to ballistic impact is of concern. While several studies document material characteristics of electronic boards under quasi-static and low impact conditions, few researchers addressed the behavior of these boards under severe impact loaDing This research presents the results of testing electronic boards under different strain rates to assess the effects of strain rates on modulus of elasticity of the boards. This work also outlines the finite element modeling methodology for these electronic components that are subjected to high acceleration loads that occur over extremely short time such as impact, gun firing and blast events. The results are used to suggest material models that can be used in finite element codes to accurately describe the impact behavior of these boards

Optimization for finite element modeling of electronic components under dynamic loaDing

Usage of electronic components in the U.S. ARMY applications is becoming more challenging due to their usage in harsh environments. Experimental verification of these components is expensive and it can yield information about specific locations only. This research outlines the finite element modeling methodology for these electronic components that are subjected to high acceleration loads that occur over extremely short time such as impact, gun firing and blast events. Due to their miniature size these finite element models are computationally expensive. An optimization engine was presented to have an efficient analysis procedure that provides a combination of accuracy, computational speed and modeling simplicity. This research also involves experimental testing of the electronic components mounted on the circuit boards. Testing was conducted at different strain levels in order to study the behavior of boards. Finite element models were developed for these tests and compared with experimental results

Development of a Rapid Fatigue Life Testing Method for Reliability Assessment of Flip-Chip Solder Interconnects

The underlying physics of failure are critical in assessing the long term reliability of power packages in their intended field applications, yet traditional reliability determination methods are largely inadequate when considering thermomechanical failures. With current reliability determination methods, long test durations, high costs, and a conglomerate of concurrent reliability degrading threat factors make effective understanding of device reliability difficult and expensive. In this work, an alternative reliability testing apparatus and associated protocol was developed to address these concerns; targeting rapid testing times with minimal cost while preserving fatigue life prediction accuracy. Two test stands were fabricated to evaluate device reliability at high frequency (60 cycles/minute) with the first being a single-directional unit capable of exerting large forces (up to 20 N) on solder interconnects in one direction. The second test stand was developed to allow for bi-directional application of stress and the integration of an oven to enable testing at elevated steady-state temperatures. Given the high frequency of testing, elevated temperatures are used to emulate the effects of creep on solder fatigue lifetime. Utilizing the mechanical force of springs to apply shear loads to solder interconnects within the devices, the reliability of a given device to withstand repeated cycling was studied using resistance monitoring techniques to detect the number of cycles-to-failure (CTF). Resistance monitoring was performed using specially designed and fabricated, device analogous test vehicles assembled with the ability to monitor circuit resistance in situ. When a resistance rise of 30 % was recorded, the device was said to have failed. A mathematical method for quantifying the plastic work density (amount of damage) sustained by the solder interconnects prior to failure was developed relying on the relationship between Hooke’s Law for springs and damage deflection to accurately assess the mechanical strength of tested devices

Design of reliable and energy-efficient high-speed interface circuits

The data-rate demand in high-speed interface circuits increases exponentially every year. High-speed I/Os are better implemented in advanced process technologies for lower-power systems, with the advantages of improved driving capability of the transistors and reduced parasitic capacitance. However, advanced technologies are not necessarily advantageous in terms of device reliability; in particular device failure from electrostatic discharge (ESD) becomes more likely in nano-scale process nodes. In order to secure ESD resiliency, the size of ESD devices on I/O pads should be sufficiently large, which may potentially reduce I/O speed. These two conflicting requirements in high-speed I/O design sometimes require sacrifice to one of the two properties. In this dissertation, three different approaches are proposed to achieve reliable and energy-efficient interface circuits. As the first approach, a novel ESD self-protection scheme to utilize “adaptive active bias conditioning” is proposed to reduce voltage stress on the vulnerable transistors, thereby reducing the burden on ESD protection devices. The second approach is to cancel out effective parasitic capacitance from ESD devices by the T-coil network. Voltage overshoot generated by magnetic coupling of the T-coil network can be suppressed by the proposed “inductance halving” technique, which reduces mutual inductance during ESD. The last approach employs system-level knowledge in the design of an ADC-based receiver for high intersymbol interference (ISI) channels. As a system-level performance metric, bit-error rate (BER) is adopted to mitigate a bit-resolution requirement in “BER-optimal ADC”, which can lead to 2× power-efficiency in the flash ADC and achieve a better BER performance

Characterization Methodology, Modeling, and Converter Design for 600 V Enhancement-Mode GaN FETs

Gallium Nitride (GaN) power devices are an emerging technology that have only become available commercially in the past few years. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This dissertation reviews the unique characteristics, commercial status, and design challenges that surround GaN FETs, in order to provide sufficient background to potential GaN-based converter designers.Methodology for experimentally characterizing a GaN FET was also presented, including static characterization with a curve tracer and impedance analyzer, as well as dynamic characterization in a double pulse test setup. This methodology was supplemented by additional tests to determine losses caused by Miller-induced cross talk, and the tradeoff between these losses and overlap losses was studied for one example device.Based on analysis of characterization results, a simplified model was developed to describe the overall switching behavior and some unique features of the device. The impact of the Miller effect during the turn-on transient was studied, as well as the dynamic performance of GaN at elevated temperature.Furthermore, solutions were proposed for several key design challenges in GaN-based converters. First, a driver-integrated overcurrent and short-circuit protection scheme was developed, based on the relationship between gate voltage and drain current in GaN gate injection transistors. Second, the limitations on maximum utilization of current and voltage in a GaN FET were studied, particularly the voltage overshoots following turn-on and turn-off switching transients, and the effective cooling of GaN FETs in higher power operation. A thermal design was developed for heat extraction from bottom-cooled surface-mount devices. These solutions were verified in a GaN-based full-bridge single-phase inverter

Thermal And Optical Performance Of Ingaalp-Based Low- And Gan-Based High-Power Light-Emitting Diode Packages

This study was divided into three main parts. In the first part, the performance of indium gallium aluminum phosphide (InGaAlP) low-power (LP) SMD LED affixed to substrates with different configurations. In the second part, the heat-dissipation factor, optical power, luminous flux, and spectral flux of LP LEDs were estimated by extending the application of the equations that were employed for high-power (HP) LEDs. In the third part, the performance of thin film gallium nitride (ThinGaN) HP LED attached to a SinkPAD via solder was evaluated

Characterisation of the cyclic softening properties of solder

Master'sMASTER OF ENGINEERIN

Low Power Skin Impedance Spectrometer

Non-invasive diagnosing is becoming a growing trend in the Medical Field, and as a result devices that do apply these non-invasive diagnoses must be developed. This project developed a medical device that measures the skin’s impedance and Phase accurately via Bluetooth graphs the results on a computer. The designed achieved is capable of measuring impedance from 200 to 3000 Ohms. This allows the project to be used for the following applications: BIA, pain sensing and diabetes diagnosis

Multi-Scale Dynamic Study of Secondary Impact During Drop Testing of Surface Mount Packages

This dissertation focuses on design challenges caused by secondary impacts to printed wiring assemblies (PWAs) within hand-held electronics due to accidental drop or impact loading. The continuing increase of functionality, miniaturization and affordability has resulted in a decrease in the size and weight of handheld electronic products. As a result, PWAs have become thinner and the clearances between surrounding structures have decreased. The resulting increase in flexibility of the PWAs in combination with the reduced clearances requires new design rules to minimize and survive possible internal collisions impacts between PWAs and surrounding structures. Such collisions are being termed ‘secondary impact’ in this study. The effect of secondary impact on board-level drop reliability of printed wiring boards (PWBs) assembled with MEMS microphone components, is investigated using a combination of testing, response and stress analysis, and damage modeling. The response analysis is conducted using a combination of numerical finite element modeling and simplified analytic models for additional parametric sensitivity studies