ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN

As the MOSFET dimensions scale down towards nanoscale level, the reliability of circuits based on these devices decreases. Hence, designing reliable systems using these nano-devices is becoming challenging. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal (RTS) noise sources to provide a more rigorous noise environment for the simulation of circuits build on nanoscale technologies. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The redesigned MRF is termed as Improved-MRF. The CMOS, MRF and Improved-MRF designs were simulated under application of highly noisy inputs. On the basis of simulations conducted for several test circuits, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives. The number of transistors, on the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF respectively (as compared to the CMOS). Therefore, in order to provide a trade-off between reliability and the area overhead required for obtaining a fault-tolerant circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this research work. The value of RAI exceeds around 1.3 and 40 times for MRF and Improved-MRF respectively as compared to CMOS design which makes Improved- MRF to be still 30 times more efficient circuit design than MRF in terms of maintaining a suitable trade-off between reliability and area-consumption of the circuit

New techniques to improve power quality and evaluate stability in modern all-electric naval ship power systems

This dissertation focuses on two crucial issues in the design and analysis of the power electronic systems on modern all-electric naval ships, i.e., power quality control and stability evaluation. It includes three papers that deal with active power filter topology, active rectifier control, and impedance measurement techniques, respectively. To mitigate harmonic currents generated by high-power high-voltage shipboard loads such as propulsion motor drives, the first paper proposes a novel seven-level shunt active power filter topology, which utilizes tapped reactors for parallel operations of switching devices. The multi-level system has been implemented in both regular digital simulation and real-time digital simulator for validation. In the second paper, a harmonic compensation algorithm for three-phase active rectifiers is proposed. Based on the theory of multiple reference frames, it provides fast and accurate regulation of selected harmonic currents so that the rectifier draws balanced and sinusoidal currents from the source, even when the input voltages are unbalanced and contain harmonics. Extensive laboratory tests on a 2 kW prototype system verifies the effectiveness of the proposed control scheme. The last paper presents a new technique for impedance identification of dc and ac power electronic systems, which significantly simplifies the procedure for stability analysis. Recurrent neural networks are used to build dynamic models of the system based on a few signal injections, then the impedance information can be extracted using off-line training and identification algorithms. Both digital simulation and hardware tests were used to validate the technique --Abstract, page iv

Technical Design Report for the PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined

A STUDY OF MRF CMOS CIRCUIT DESIGN IMPLEMENTATION

Shrinking devices to the smaller scale and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. One possible solution for this matter is to have a paradigm shift to a fault tolerant probabilistic framework. Probabilistic computing provides a new approach towards building fault-tolerant architectures and systems. The logic states are considered to be random variables. Under this framework, one no longer expects a correct logic signal at all nodes at all times, but only that the joint probability distribution of signal values has the highest likelihood for valid logic states. The probabilistic approach is based on the theory of Markov Random Fields (MRF), which is extensible to a large number of logic variables. This theory can be used to design the circuit with high noise immunity. This report discusses about the inverter circuits, and comparison between the obtained results for both MRF and Standard inverters using Cadence tools and MA TLAB in both noisy and ideal conditions. The results are in micro-regime, since the minimum dimensions of the software were in micro-ranges. The project focused more on the analysis of noise for both inverters and the transistors inside each one of them. As a result of completing the above procedure, it was proved that MRF inverter is tolerant to noisy conditions where as the standard inverter is not

Innovative magnetorheological devices for shock and vibration mitigation

Vibration and impact protection have been a popular topic in research fields, which could directly affect the passengers’ and drivers’ comfort and safety, even cause spines fracture. Therefore, an increasing number of vehicle suspensions and aircraft landing gears are proposed and manufactured. Magnetorheological fluids (MRFs), as a smart material, are growly applied into the above device owing to its unique properties such as fast response, reversible properties, and broad controllable range, which could improve the vibration/impact mitigation performance. MRF was utilized to achieve adaptive parameters of the vehicle suspensions by controlling the magnetic field strength of the MRF working areas. Generally, the magnetic field is provided by a given current, subsequently, it would consume massive energy from a long-term perspective. Thus, a self-powered concept was applied as well. This thesis reports a compact stiffness controllable MR damper with a self-powered capacity. After the prototype of the MR damper, its property tests were conducted to verify the stiffness controllability and the energy generating ability using a hydraulic Instron test system. Then, a quarter-car test rig was built, and the semi-active MR suspension integrated with the self-powered MR damper was installed on a test rig. Two controllers, one based on short-time Fourier transform (STFT) and a classical skyhook controller was developed to control the stiffness. The evaluation results demonstrate that the proposed MR damper incorporated with STFT controller or skyhook controller could suppress the response displacements and accelerations obviously comparing with the conventional passive systems

ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN

As the MOSFET dimensions scale down towards nanoscale level, the reliability of circuits based on these devices decreases. Hence, designing reliable systems using these nano-devices is becoming challenging. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal (RTS) noise sources to provide a more rigorous noise environment for the simulation of circuits build on nanoscale technologies. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The redesigned MRF is termed as Improved-MRF. The CMOS, MRF and Improved-MRF designs were simulated under application of highly noisy inputs. On the basis of simulations conducted for several test circuits, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives. The number of transistors, on the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF respectively (as compared to the CMOS). Therefore, in order to provide a trade-off between reliability and the area overhead required for obtaining a fault-tolerant circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this research work. The value of RAI exceeds around 1.3 and 40 times for MRF and Improved-MRF respectively as compared to CMOS design which makes Improved- MRF to be still 30 times more efficient circuit design than MRF in terms of maintaining a suitable trade-off between reliability and area-consumption of the circuit

Self-Healing Cellular Automata to Correct Soft Errors in Defective Embedded Program Memories

Static Random Access Memory (SRAM) cells in ultra-low power Integrated Circuits (ICs) based on nanoscale Complementary Metal Oxide Semiconductor (CMOS) devices are likely to be the most vulnerable to large-scale soft errors. Conventional error correction circuits may not be able to handle the distributed nature of such errors and are susceptible to soft errors themselves. In this thesis, a distributed error correction circuit called Self-Healing Cellular Automata (SHCA) that can repair itself is presented. A possible way to deploy a SHCA in a system of SRAM-based embedded program memories (ePM) for one type of chip multi-processors is also discussed. The SHCA is compared with conventional error correction approaches and its strengths and limitations are analyzed

Harmonic compensation in a grid using doubly fed induction generators

Ideally, electric utilities are expected to deliver a sinusoidal voltage with a constant rated frequency, while customers are expected to draw a sinusoidal current with unity power factor. The recent widespread use of harmonic producing equipment in industrial applications, especially non-linear loads, has increased the distortion of electric currents and voltages in transmission and distribution systems. This thesis proposes a method of using multiple reference frame theory for measuring and mitigating harmonic currents of nonlinear loads using a doubly fed induction generator. The most significant low-order harmonics to be compensated are calculated using a multiple reference frame harmonic observer. This observer is simulated using Matlab® Simulink® and then implemented using the Texas Instruments TMS320F28335 digital signal processor. Experimental and simulation results are provided to verify the analysis of the observer by comparing the results with calculations from the Fourier spectrum. Along with active and reactive power generation, an algorithm is proposed to inject currents in the rotor for the mitigation of harmonics in the system. Simulation results are presented to demonstrate the performance of this proposed method. These results validate the effectiveness of the method in compensating the targeted harmonics in the system. This method of measuring and compensating harmonics discussed in this thesis is accurate, straightforward, easily implemented and effective in the mitigation of any harmonic in the system. The currents obtained in the fundamental reference frame can be further employed for the control of active and reactive power flow --Abstract, page iii

Frequency Translation loops for RF filtering-Theory and Design

Modern wireless transceivers are required to operate over a wide range of frequencies in order to support the multitude of currently available wireless standards. Wideband operation also enables future systems that aim for better utilization of the available spectrum through dynamic allocation. As such, co-existence problems like harmonic mixing and phase noise become a main concern. In particular, dealing with interfer- ence scenarios is crucial since they directly translate to higher linearity requirements in a receiver. With CMOS driving the consumer electronics market due to low cost and high level of integration demands, the continued increase in speed, mainly intended for digital applications, oers new possibilities for RF design to improve the linearity of front-end receivers. Furthermore, the readily available switches in CMOS have proven to be a viable alternative to traditional active mixers for frequency translation due to their high linearity, low flicker noise, and, most recently recognized, their impedance transformation properties. In this thesis, frequency translation feedback loops employing passive mixers are explored as a means to relax the linearity requirements in a front-end receiver by providing channel selectivity as early as possible in the receiver chain. The proposed receiver architecture employing such loop addresses some of the most common prob- lems of integrated RF lters, while maintaining their inherent tunability. Through a simplied and intuitive analysis, the operation of the receiver is first examined and the design parameters aecting the lter characteristics, such as band- width and stop-band rejection, are determined. A systematic procedure for analyzing the linearity of the receiver reveals the possibility of LNA distortion canceling, which decouples the trade-o between noise, linearity and harmonic radiation. Next, a detailed analysis of frequency translation loops using passive mixers is developed. Only highly simplied analysis of such loops is commonly available in literature. The analysis is based on an iterative procedure to address the complexity introduced by the presence of LO harmonics in the loop and the lack of reverse isolation in the mixers, and results in highly accurate expressions for the harmonic and noise transfer functions of the system. Compared to the alternative of applying general LPTV theory, the procedure developed oers more intuition into the operation of the system and only requires the knowledge of basic Fourier analysis. The solution is shown to be capable of predicting trade-os arising due to harmonic mixing and loop stability requirements, and is therefore useful for both system design and optimization. Finally, as a proof of concept, a chip prototype is designed in a standard 65nm CMOS process. The design occupies +12dBm. As such, the work presented in this thesis aims to provide a highly-integrated means for programmable RF channel selection in wideband receivers. The topic oers several possibilities for further research, either in terms of extending the viability of the system, for example by providing higher order ltering, or by improving performance, such as noise