8 research outputs found
Quantifiable Assurance: From IPs to Platforms
Hardware vulnerabilities are generally considered more difficult to fix than
software ones because they are persistent after fabrication. Thus, it is
crucial to assess the security and fix the vulnerabilities at earlier design
phases, such as Register Transfer Level (RTL) and gate level. The focus of the
existing security assessment techniques is mainly twofold. First, they check
the security of Intellectual Property (IP) blocks separately. Second, they aim
to assess the security against individual threats considering the threats are
orthogonal. We argue that IP-level security assessment is not sufficient.
Eventually, the IPs are placed in a platform, such as a system-on-chip (SoC),
where each IP is surrounded by other IPs connected through glue logic and
shared/private buses. Hence, we must develop a methodology to assess the
platform-level security by considering both the IP-level security and the
impact of the additional parameters introduced during platform integration.
Another important factor to consider is that the threats are not always
orthogonal. Improving security against one threat may affect the security
against other threats. Hence, to build a secure platform, we must first answer
the following questions: What additional parameters are introduced during the
platform integration? How do we define and characterize the impact of these
parameters on security? How do the mitigation techniques of one threat impact
others? This paper aims to answer these important questions and proposes
techniques for quantifiable assurance by quantitatively estimating and
measuring the security of a platform at the pre-silicon stages. We also touch
upon the term security optimization and present the challenges for future
research directions
Kiel Declarative Programming Days 2013
This report contains the papers presented at the Kiel Declarative Programming Days 2013, held in Kiel (Germany) during September 11-13, 2013. The Kiel Declarative Programming Days 2013 unified the following events: * 20th International Conference on Applications of Declarative Programming and Knowledge Management (INAP 2013) * 22nd International Workshop on Functional and (Constraint) Logic Programming (WFLP 2013) * 27th Workshop on Logic Programming (WLP 2013) All these events are centered around declarative programming, an advanced paradigm for the modeling and solving of complex problems. These specification and implementation methods attracted increasing attention over the last decades, e.g., in the domains of databases and natural language processing, for modeling and processing combinatorial problems, and for high-level programming of complex, in particular, knowledge-based systems
Efficient Preimage Computation Using A Novel Success-Driven ATPG
Preimage computation is a key step in formal verification. Pure OBDD-based symbolic method is vulnerable to the space-explosion problem. On the other hand, conventional ATPG/SAT-based method can handle large designs but can suffer from time explosion. Unlike methods that combine ATPG/SAT and OBDD, we present a novel success-driven learning algorithm which significantly accelerates a ATPG engine for enumerating all solutions (preimages). The algorithm effectively prunes redundant search space due to overlapped solutions and constructs a free BDD on the fly so that it becomes the representation of the preimage set at the end. Experimental results have demonstrated the effectiveness of the approach, in which we are able to compute preimages for large sequential circuits, where OBDD-based method fail