SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylindrical surrounding gate MOSFET

We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub-10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length Lg and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current method is used to define the threshold voltage as the gate voltage at a constant current, (2πR/Lg)10-7 A for channel length and channel radius R. The central potential of the JLCSG MOSFET is determined by the Poisson equation. As a result, it can be seen that the DIBL of the JLCSG MOSFET is proportional to the –2.76 power of the channel length, to the 1.76 power of the channel radius, and linearly to the oxide film thickness. At this time, we observe that the SPICE parameter, the static feedback coefficient, has a value less than 1 1, and this model can be used to analyze the DIBL of the JLCSG MOSFET

Design and analytical performance of subthreshold characteristics of CSDG MOSFET.

Masters Degree. University of KwaZulu-Natal, Durban.The downscaling of the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) devices have been the driving force for Nanotechnology and Very Large-Scale Integration (VLSI) systems. This is affirmed by Moore’s law which states that “The number of transistors placed in an Integrated Circuit (IC) or chip doubles approximately every two years”. The main objectives for the transistor scaling are: to increase functionality, switching speed, packing density and lower the operating power of the ICs. However, the downscaling of the MOSFET device is posed with various challenges such as the threshold roll-off, Drain Induced Barrier Lowing (DIBL), surface scattering, and velocity saturation known as Short Channel Effects (SCEs). To overcome these challenges, a cylindrically structured MOSFET is employed because it increases the switching speed, current flow, packing density, and provides better immunity to SCEs. This thesis proposes a Cylindrical Surrounding Double-Gate (CSDG) MOSFET which is an extended version of Double-Gate (DG) MOSFET and Cylindrical Surrounding-Gate (CSG) MOSFET in terms of form factor and current drive respectively. Furthermore, employing the Evanescent-Mode analysis (EMA) of a two-dimensional (2D) Poisson solution, the performance analysis of the novel CSDG MOSFET is presented. The channel length, radii Silicon film difference, and the oxide thickness are investigated for the CSDG MOSFET at the subthreshold regime. Using the minimum channel potential expression obtained by EMA, the threshold voltage and the subthreshold swing model of the proposed CSDG MOSFET are evaluated and discussed. The device performance is verified with various values of radii Silicon film difference and gate oxide thickness Finally, the low operating power and switching characteristics of the proposed CSDG MOSFET has been employed to design a simple CSDG bridge rectifier circuit for micropower electricity (energy harvester). Similar to the traditional MOSFETs, the switching process of CSDG MOSFET is in two operating modes: switch-ON (conduction of current between the drain and source) or switched-OFF (no conduction of current). However, unlike the traditional diode bridge rectifier which utilizes four diodes for its operation, the CSDG bridge rectifier circuits employs only two CSDGs (n-channel and p- channel) for its operation. This optimizes cost and improves efficiency. Finally, the results from the analyses demonstrate that the proposed CSDG MOSFET is a promising device for nanotechnology and self-micro powered device system application

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO2/high-k dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second derivative method to obtain the on-current. As a result, this model agrees with the results from other papers. The on-off current ratio is in proportion to the arithmetic average of the upper and lower high dielectric material thicknesses. The on-off current ratio of 104 or less is shown for SiO2, but the on-off current ratio for TiO2 (k=80) increases to 107 or more

Analytical model of subthreshold swing in junctionless gate-all-around (GAA) FET with ferroelectric

An analytical SS model is presented to observe the subthreshold swing (SS) of a junctionless gate-all-around (GAA) FET with ferroelectric in this paper. For the gate structure, a multilayer structure of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) was used, and the SS was calculated in $15 \leqslant {P_r} \leqslant 30\,\mu C/c{m^2}$ and $0.8 \leqslant {E_c} \leqslant 1.5\,MV/cm$, which are the ranges of remanent polarization and coercive field suggested in various experiments in the case of HZO as the ferroelectric material. It was found that the SSs from the presented analytical SS model agree well with those derived from the relationship between drain current and gate voltage using a 2D potential distribution in the range of device parameters used for simulation. As a result of analyzing the SS of the junctionless GAA FET with ferroelectric using the analytical SS model presented in this paper, the SS decreased because the voltage across the inner gate decreased when the ferroelectric thickness increased. It was observed that the condition of SS < 60 mV/dec was sufficiently obtained according to changes in device parameters such as channel length, channel radius and ferroelectric thickness, and that the SS maintained a constant value according to the ratio of remanent polarization and coercive field Pr/Ec. As Pr/Ec increases, the SS increases as the ferroelectric capacitance increases. As the channel length becomes smaller, the change in SS according to Pr/Ec is more severe

Vertical Integration of Germanium Nanowires on Silicon Substrates for Nanoelectronics.

Rapid development of semiconductor industry in recent years has been primarily driven by continuous scaling. As the size of the transistors approaches tens of nanometers, we are faced with challenges due to technological and economic reasons. To this end, unconventional semiconductor materials and novel device structures have attracted a lot of interests as promising candidates to replace the Si-channel MOSFET and help extend Moore’s law. In this dissertation, we focus on chemically-synthesized germanium nanowires, and investigate their potential as electronic devices, especially when vertically integrated on a Si substrate. The contributions of the work are as follows: First, the Vapor-Liquid-Solid method for growing Ge nanowires on (111) Si substrates is explored. In addition to the growth of vertical, taper-free, intrinsic Ge nanowires, strategies for doping the nanowires, forming a radial heterojunction and controlling growth sites are also discussed. Second, the Ge/Si heterojunction obtained via nanowire growth is examined by transmission electron microscopy. We confirm the epitaxial nature of the heterojunction despite the 4% lattice mismatch and determine the transition width to be 10-15 nm. Vertical heterodiodes with independently-tuned doping profile in both Ge and Si are demonstrated. Different devices are obtained, including: (1) a rectifying diode with >1,000,000 on/off ratio and ideality factor of 1.16; (2) a tunnel diode with room temperature negative differential resistance, peak current density of 4.57 kA/cm2 and reversed-bias tunnel current of 3.2 µA/µm; (3) a non-ohmic contact due to large valence band offset between Ge and Si. All observed behaviors are very well supported by theoretical analysis of the devices. In addition, a vertical junctionless transistor with Ge/Si core/shell nanowire channel and surrounding gate is demonstrated. High performance p-type transistor behavior with on state current density of 750 µA/µm and mobility of 282 cm2/V∙s is achieved. Moreover, an analytical model is developed to quantitatively explain the measured data and excellent agreement is obtained. Finally, progress towards the realization of a nanowire tunnel transistor is reported. A physical model for nanowire tunnel transistors is proposed. Preliminary experimental results verified that the device concept works although further optimization is still required to boost its performance.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/120872/1/linchen_1.pd

Modeling and analysis of cylindrical gate-all around silicon nanowire FET including BOHM quantum potential model

According to Moores’s Law, the number of transistors per square inch on integrated circuits are doubled every year. Now, the transistors size has been scaled down to 15nm. The smaller the transistors size gives more space for transistors to be added in system on chip (SoC) thus will provide a lot of functionality. This can be fundamentally viewed as mechanism leads to deviation of the functional behavior from its ideal case. However, the reduction of channel length into nanometer regime would cause short channel effects (SCEs). New transistor device architecture such as gate-all-around silicon nanowire (GAASiNW) field-effect-transistor (FET) is believed to be a promising future device to solve the scaling problem especially SCEs. GAASiNW is proved to be more immune to SCEs compared to conventional FET. Due to continuous device scaling, quantum effects cannot be neglected especially with today’s technology has reaching 10nm technology node. It has been pointed out by previous researchers that quantum effect such as tunneling effect has become one of the fundamental limitation to accurately describe the charge distribution in GAA SiNW. In this research project, an analytic carrier models in conducting channel for improving electrical characteristic of GAASiNW is investigated. One major focus of this study is to enhance fundamental understanding of quantum effect in an optimized GAASiNW FET device by investigating in details how these quantum effects influence device’s electrical characteristics. The study of quantum effect and comparison between quantum models on GAASiNW FET are compared. The study are conducted by using 3-D TCAD tools. The analytic drift-diffusion including Bohm quantum potential (BQP) model are carried out as its device carrier transport. It is proved that the proposed GAASiNW device with BQP model as the carrier transport able to reduce the DIBL by 83% when applying a low doped at S/D region. In fact, the proposed GAASiNW FET model with BQP model shows a good electrical characteristic when the channel length is scaled to 20 and 16nm

ANALYTICAL COMPACT MODELING OF NANOSCALE MULTIPLE-GATE MOSFETS.

L’objectiu principal d’aquest treball és el desenvolupament d’un model compacte per a MOSFETs de múltiple porta d’escala nanomètrica, que sigui analític, basat en la física del dispositiu, i predictiu per a simulacions AC i DC. Els dispositius investigats són el MOSFET estàndar en mode d’inversió, a més d’un nou dispositiu anomenat “junctionless MOSFET” (MOSFET sense unions). El model es va desenvolupar en una formulació compacta amb l’ajuda de l’equació de Poisson i la tècnica de la transformación conforme de Schwarz-Cristoffel. Es varen obtenir les equacions del voltatge llindar i el pendent subllindar. Usant la funció W de Lambert, a més d’una funció de suavització per a la transcició entre les regions de depleció i acumulació, s’obté un model unificat de la densitat de càrrega, vàlid per a tots els modes d’operació del transistor. S’estudien també les dependències entre els paràmetres físics del dispositiu i el seu impacte en el seu rendiment. Es tenen en compteefectes importants de canal curt i de quantització. Es discuteixen també la simetria al voltant de Vds= 0 V, i la continuïtat del corrent de drenador en les derivades d’ordre superior. El model va ser validat mitjançant simulacions TCAD numèriques i mesures experimentals.El objetivo principal de este trabajo es el desarrollo de un modelo compacto para MOSFETs de múltiple puerta de escala nanométrica, que sea analítico, basado en la física del dispositivo, y predictivo para simulaciones AC y DC. Los dispositivos investigados son el MOSFET estándar en modo inversión, además de un nuevo dispositivo llamado “junctionless MOSFET” (MOSFET sin uniones). El modelo se desarrolló en una formulación compacta con la ayuda de la ecuación de Poisson y la técnica de transformación conforme de Schwarz-Cristoffel. Se obtuvieron las ecuaciones del voltaje umbral y la pendiente subumbral. Usando la función W de Lambert, además de una función de suavización para la transición entre las regiones de depleción y acumulación, se obtiene un modelo unificado de la densidad de carga, válido para todos los modos de operación del transistor. Se estudian también las dependencias entre los parámetros físicos del dispositivo y su impacto en su rendimiento. Se tienen en cuenta efectos importantes de canal corto y de cuantización. Se discuten también la simetría alrededor de Vds= 0 V, y la continuidad de la corriente de drenador en las derivadas de orden superior. El modelo fue validado mediante simulaciones TCAD numéricas y medidas experimentales.The main focus is on the development of an analytical, physics-based and predictive DC and AC compact model for nanoscale multiple-gate MOSFETs. The investigated devices are the standard inversion mode MOSFET and a new device concept called junctionless MOSFET. The model is derived in closed-from with the help of Poisson's equation and the conformal mapping technique by Schwarz-Christoffel. Equations for the calculation of the threshold voltage and subthreshold slope are derived. Using Lambert's W-function and a smoothing function for the transition between the depletion and accumulation region, an unified charge density model valid for all operating regimes is developed. Dependencies between the physical device parameters and their impact on the device performance are worked out. Important short-channel and quantization effects are taken into account. Symmetry around Vds = 0 V and continuity of the drain current at derivatives of higher order are discussed. The model is validated versus numerical TCAD simulations and measurement data

Charge-based compact model of gate-all-around floating gate nanowire with variable oxide thickness for flash memory cell

Due to high gate electrostatic control and introduction of punch and plug process technology, the gate-all-around (GAA) transistor is very promising in, and apparently has been utilized for, flash memory applications. However, GAA Floating Gate (GAA-FG) memory cell still requires high programming voltage that may be susceptible to cell-to-cell interference. Scaling down the tunnel oxide can reduce the Program/Erase (P/E) voltage but degrades the data retention capability. By using Technology-Computer-Aided-Design (TCAD) tools, the concept of tunnel barrier engineering using Variable Oxide Thickness (VARIOT) of low-k/high-k stack is utilized in compensating the trade-off between P/E operation and retention characteristics. Four high-k dielectrics (Si3N4, Al2O3, HfO2 and ZrO2) that are commonly used in semiconductor process technology are examined with SiO2 as its low-k dielectric. It is found that by using SiO2/Al2O3 as the tunnel layer, both the P/E and retention characteristics of GAA-FG can be compensated. About 30% improvement in memory window than conventional SiO2 is obtained and only 1% of charge-loss is predicted after 10 years of applying gate stress of -3.6V. Compact model of GAA-FG is initiated by developing a continuous explicit core model of GAA transistor (GAA Nanowire MOSFET (GAANWFET) and Juntionless Nanowire Transitor (JNT)). The validity of the theory and compact model is identified based on sophisticated numerical TCAD simulator for under 10% maximum error of surface potential. It is revealed that with the inclusion of partial-depletion conduction, the accuracy of the core model for GAANWFET is improved by more than 50% in the subthreshold region with doping-geometry ratio can be as high as about 0.86. As for JNT, despite the model being accurate for doping-geometry ratio upto 0.6, it is also independent of fitting parameters that may vary under different terminal biases or doping-geometry cases. The compact model of GAA-FG is completed by incorperating Charge Balance Model (CBM) into GAA transistor core model where good agreement is obtained with TCAD simulation and published experimental work. The CBM gives better accuracy than the conventional capacitive coupling approach under subthreshold region with approximately 10% error of floating gate potential. Therefore, the proposed compact model can be used to assist experimental work in extracting experimental data

Analytical Modeling of Ultrashort-Channel MOS Transistors

Les geometries de transistors d'avui són al rang de nanòmetres d'un sol dígit. En conseqüència, les funcionalitats dels dispositius es veuen afectades negativament pels efectes de canal curt i de mecànica quàntica (SCE i QMEs). Una transició de la geometria del transistor d'efecte de camp de tipus FinFET a Gate-All-Around (GAA) FETs com FETs de nanofils cilíndrics (NW) i de nanoplaques de silici (SiNS) es preveuen en els propers nodes tecnològics per suprimir els SCE i garantir una major miniaturització del MOSFET Aquesta dissertació se centra en el modelat analític de FETs de tipus NW i SiNS de canal ultracurt.S'introdueix un concepte de dimensions de doble porta (DG) equivalent per transferir un model de potencial de DG analític a FET de NW. Un model de corrent de DG compacte es modifica aprofitant la simetria rotacional dels FET de NW. L'efecte del confinament quàntic (QC) és implementat considerant l'eixamplament addicional de la banda prohibida al càlcul d'una concentració de portadors de càrrega intrínseca efectiva i al càlcul del voltatge llindar. L'efecte de corrent túnel directe de font a drenador (DSDT) a SiNS FET ultraescalats es modela amb el nou mètode de wavelets. Aquest model calcula analíticament la probabilitat de tunelització per a cada energia de l'electró, aproximant la forma de la barrera potencial mitjançant una barrera rectangular amb una altura de barrera equivalent. A causa de la fórmula de corrent túnel de Tsu-Esaki no analíticament integrable, es presenta un mètode analític anomenat model quasi-compacte (QCM). Aquest enfocament requereix, entre altres aproximacions, una iteració de Newton i una interpolació lineal de la densitat de corrent amb efecte túnel. A més, es realitza una anàlisi criogènica de temperatura i dopatge. S'investiga la forta influència de la distància del nivell de Fermi a la font des de la vora de la banda de conducció sobre el pendent subumbral, el corrent i la reducció de la barrera induïda per drenador (DIBL). A més, es demostra i explica la fusió de dos efectes relacionats amb el pendent subumbral i el DIBL. La validesa del concepte de dimensions DG equivalents es demostra mitjançant el mesurament i les dades de simulació de TCAD Sentaurus, mentre que el mètode de wavelets es verifica mitjançant simulacions NanoMOS NEGF.Las geometrías de transistores de hoy están en el rango de nanómetros de un solo dígito. En consecuencia, las funcionalidades de los dispositivos se ven afectadas negativamente por los efectos de canal corto y de mecánica cuántica (SCE y QMEs). Una transición de la geometría del transistor de efecto de campo de tipo FinFET a Gate-All -Around (GAA) FETs tales como FETs de nanohilos cilíndricos (NW) y de nanoplacas de silicio (SiNS) se prevén en los próximos nodos tecnológicos para suprimir los SCE y garantizar una mayor miniaturización del MOSFET. Esta disertación se centra en el modelado analítico de FETs de tipo NW y SiNS de canal ultracorto. Se introduce un concepto de dimensiones de doble puerta (DG) equivalente para transferir un modelo de potencial de DG analítico a FET de NW. Un modelo de corriente de DG compacto se modifica aprovechando la simetría rotacional de los FET de NW. El efecto del confinamiento cuántico (QC) es implementado considerando el ensanchamiento adicional de la banda prohibida en el cálculo de una concentración de portadores de carga intrínseca efectiva y en el cálculo del voltaje de umbral. El efecto de corriente túnel directa de fuente a drenador (DSDT) en SiNS FET ultraescalados se modela con el nuevo método de wavelets. Este modelo calcula analíticamente la probabilidad de tunelización para cada energía del electrón aproximando la forma de la barrera de potencial mediante una barrera rectangular con una altura de barrera equivalente. Usando la fórmula de corriente túnel de Tsu-Esaki no analíticamente integrable, se presenta un método analítico denominado modelo cuasi-compacto (QCM), querequiere una iteración de Newton y una interpolación lineal de la densidad de corriente de efecto túnel. Además, se realiza un análisis criogénico en temperatura y dopaje. Se investiga la fuerte influencia del nivel de Fermi de la fuente la sobre la pendiente subumbral, la corriente y la reducción del efecto DIBL. Además, se demuestra y explica la fusión de dos efectos relacionados con la pendiente subumbral y el DIBL. La validez del concepto de dimensiones DG equivalentes se demuestra mediante datos de mediciones y de simulaciones TCAD Sentaurus, mientras que el método de wavelets se verifica mediante simulaciones NanoMOS NEGF.Today's transistor geometries are in the single-digit nanometer range. Consequently, device functionalities are negatively affected by short-channel and quantum mechanical effects (SCEs & QMEs). A transition from fin field-effect transistor (FinFET) geometry to gate-all-around (GAA) FETs such as cylindrical nanowire (NW) and silicon nanosheet (SiNS) FETs is envisioned in the upcoming technology nodes to suppress SCEs and ensure further MOSFET miniaturization. This dissertation focuses on the analytical modeling of ultrashort-channel NW and SiNS FETs. An equivalent double-gate (DG) dimensions concept is introduced to transfer an analytical DG potential model to NW FETs. A compact DG current model is modified by exploiting the rotational symmetry of NW FETs. The effect of quantum confinement (QC) is implemented by considering the additional bandgap widening in the calculation of an effective intrinsic charge carrier concentration and in the calculation of the threshold voltage. The effect of direct source-to-drain tunneling (DSDT) current in ultrascaled SiNS FETs is modeled with the new wavelet approach. This model calculates the tunneling probability analytically for each electron energy by approximating the potential barrier shape by a rectangular barrier with an equivalent barrier height. Due to the nonanalytically integrable Tsu-Esaki tunneling formula an analytical approach named quasi-compact model (QCM) is presented. This approach requires, among other approximations, a Newton iteration, and a linear interpolation of the tunneling current density. Furthermore, a cryogenic temperature and doping analysis is performed. The strong influence of the distance of the source related Fermi level from the conduction band edge on the subthreshold swing, current, and drain-induced barrier lowering (DIBL) saturation is investigated. Also, the merging of two subthreshold swing and DIBL effects is demonstrated and explained. The validity of the equivalent DG dimensions concept is proven by measurement and TCAD Sentaurus simulation data, while the wavelet approach is verified by NanoMOS NEGF simulations

Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology is facing great challenges to overcome severe short-channel effects. Multigate MOSFETs are one of the most promising candidates for scaling beyond Si CMOS, due to better electrostatic control as compared to conventional planar MOSFETs. Conventional dry etching-induced surface damage is one of the main sources of performance degradation for multigate transistors, especially for III-V high mobility materials. It is also challenging to increase the fin aspect ratio by dry etching because of the non-ideal anisotropic etching profile. Here, we report a novel method, inverse metal-assisted chemical etching (i-MacEtch), in lieu of conventional RIE etching, for 3D fin channel formation. InP junctionless FinFETs with record high-aspect-ratio (~ 50:1) fins are demonstrated by this method for the first time. The i-MacEtch process flow eliminates dry-etching-induced plasma damage, high energy ion implantation damage, and high temperature annealing, allowing for the fabrication of InP fin channels with atomically smooth sidewalls. The sidewall features resulting from this unique and simplified process ensure high interface quality between high-k dielectric layer and InP fin channel. Experimental and theoretical analyses show that high-aspect-ratio FinFETs, which could deliver more current per area under much relaxed horizontal geometry requirements, are promising in pushing the technology node ahead where conventional scaling has met its physical limits. The performance of the FinFET was further investigated through numerical simulation. A new kind of FinFET with asymmetric gate and source/drain contacts has been proposed and simulated. By benchmarking with conventional symmetric FinFET, better short-channel behavior with much higher current density is confirmed. The design guidelines are provided. The overall circuit delay can be minimized by optimizing gate lengths according to different local parasites among circuits in interconnection-delay-dominated SoC applications. Continued transistor scaling requires even stronger gate electrostatic control over the channel. The ultimate scaling structure would be gate-all-around nanowire MOSFETs. We demonstrate III-V junctionless gate-all-around (GAA) nanowire (NW) MOSFETs for the first time. For the first time, source/drain (S/D) resistance and thermal budget are minimized by regrowth using metalorganic chemical vapor deposition (MOCVD) in III-V MOSFETs. The fabricated short-channel (Lg=80 nm) GaAs GAA NWFETs with extremely narrow nanowire width (WNW= 9 nm) show excellent transconductance (gm) linearity at biases (300 mV), characterized by the high third intercept point (2.6 dBm). The high linearity is especially important for low power applications because it is insensitive to bias conditions