Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

Circuits and Systems Advances in Near Threshold Computing

Modern society is witnessing a sea change in ubiquitous computing, in which people have embraced computing systems as an indispensable part of day-to-day existence. Computation, storage, and communication abilities of smartphones, for example, have undergone monumental changes over the past decade. However, global emphasis on creating and sustaining green environments is leading to a rapid and ongoing proliferation of edge computing systems and applications. As a broad spectrum of healthcare, home, and transport applications shift to the edge of the network, near-threshold computing (NTC) is emerging as one of the promising low-power computing platforms. An NTC device sets its supply voltage close to its threshold voltage, dramatically reducing the energy consumption. Despite showing substantial promise in terms of energy efficiency, NTC is yet to see widescale commercial adoption. This is because circuits and systems operating with NTC suffer from several problems, including increased sensitivity to process variation, reliability problems, performance degradation, and security vulnerabilities, to name a few. To realize its potential, we need designs, techniques, and solutions to overcome these challenges associated with NTC circuits and systems. The readers of this book will be able to familiarize themselves with recent advances in electronics systems, focusing on near-threshold computing

Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.PhDGee-Kung Chang - Committee Chair; Chang-Ho Lee - Committee Member; Geoffrey Ye Li - Committee Member; Paul A. Kohl - Committee Member; Shyh-Chiang Shen - Committee Membe

Diseño CMOS de un sistema de visión “on-chip” para aplicaciones de muy alta velocidad

Falta palabras claveEsta Tesis presenta arquitecturas, circuitos y chips para el diseño de sensores de visión CMOS con procesamiento paralelo embebido. La Tesis reporta dos chips, en concreto: El chip Q-Eye; El chip Eye-RIS_VSoC.. Y dos sistemas de visión construidos con estos chips y otros sistemas “off-chip” adicionales, como FPGAs, en concreto: El sistema Eye-RIS_v1; El sistema Eye-RIS_v2. Estos chips y sistemas están concebidos para ejecutar tareas de visión a muy alta velocidad y con consumos de potencia moderados. Los sistemas resultantes son, además, compactos y por lo tanto ventajosos en términos del factor SWaP cuando se los compara con arquitecturas convencionales formadas por sensores de imágenes convencionales seguidos de procesadores digitales. La clave de estas ventajas en términos de SWaP y velocidad radica en el uso de sensores-procesadores, en lugar de meros sensores, en la interface de los sistemas de visión. Estos sensores-procesadores embeben procesadores programables de señal-mixta dentro del pixel y son capaces tanto de adquirir imágenes como de pre-procesarlas para extraer características, eliminar información redundante y reducir el número de datos que se transmiten fuera del sensor para su procesamiento ulterior. El núcleo de la tesis es el sensor-procesador Q-Eye, que se usa como interface en los sistemas Eye-RIS. Este sensor-procesador embebe una arquitectura de procesamiento formada por procesadores de señal-mixta distribuidos por pixel. Sus píxeles son por tanto estructuras multi-funcionales complejas. De hecho, son programables, incorporan memorias e interactúan con sus vecinos para realizar una variedad de operaciones, tales como: Convoluciones lineales con máscaras programables; Difusiones controladas por tiempo y nivel de señal, a través de un “grid” resistivo embebido en el plano focal; Aritmética de imágenes; Flujo de programación dependiente de la señal; Conversión entre los dominios de datos: imagen en escala de grises e imagen binaria; Operaciones lógicas en imágenes binarias; Operaciones morfológicas en imágenes binarias. etc. Con respecto a otros píxeles multi-función y sensores-procesadores anteriores, el Q-Eye reporta entre otras las siguientes ventajas: Mayor calidad de la imagen y mejores prestaciones de las funcionalidades embebidas en el chip; Mayor velocidad de operación y mejor gestión de la energía disponible; Mayor versatilidad para integración en sistemas de visión industrial. De hecho, los sistemas Eye-RIS son los primeros sistemas de visión industriales dotados de las siguientes características: Procesamiento paralelo distribuido y progresivo; Procesadores de señal-mixta fiables, robustos y con errores controlados; Programabilidad distribuida. La Tesis incluye descripciones detalladas de la arquitectura y los circuitos usados en el pixel del Q-Eye, del propio chip Q-Eye y de los sistemas de visión construidos en base a este chip. Se incluyen también ejemplos de los distintos chips en operaciónThis Thesis presents architectures, circuits and chips for the implementation of CMOS VISION SENSORS with embedded parallel processing. The Thesis reports two chips, namely: Q-eye chip; Eye-RIS_VSoC chip, and two vision systems realized by using these chips and some additional “off-chip” circuitry, such as FPGAs. These vision systems are: Eye-RIS_v1 system; Eye-RIS_v2 system. The chips and systems reported in the Thesis are conceived to perform vision tasks at very high speed and with moderate power consumption. The proposed vision systems are also compact and advantageous in terms of SWaP factors as compared with conventional architectures consisting of standard image sensor followed by digital processors. The key of these advantages in terms of SWaP and speed lies in the use of sensors-processors, rather than mere sensors, in the front-end interface of vision systems. These sensors-processors embed mixed-signal programmable processors inside the pixel. Therefore, they are able to acquire images and process them to extract the features, removing the redundant information and reducing the data throughput for later processing. The core of the Thesis is the sensor-processor Q-Eye, which is used as front-end in the Eye-RIS systems. This sensor-processor embeds a processing architecture composed by mixed-signal processors distributed per pixel. Then, its pixels are complex multi-functional structures. In fact, they are programmable, incorporate memories and interact with its neighbors in order to carry out a set of operations, including: Linear convolutions with programmable linear masks; Time- and signal-controlled diffusions (by means of an embedded resistive grid); Image arithmetic; Signal-dependent data scheduling; Gray-scale to binary transformation; Logic operation on binary images; Mathematical morphology on binary images, etc. As compared with previous multi-function pixels and sensors-processors, the Q-Eye brings among other the following advantages: Higher image quality and better performances of functionalities embedded on chip; Higher operation speed and better management of energy budget; More versatility for integration in industrial vision systems. In fact, the Eye-RIS systems are the first industrial vision systems equipped with the following characteristics: Parallel distributed and progressive processing; Reliable, robust mixed-signal processors with handled errors; Distributed programmability. This Thesis includes detailed descriptions of architecture and circuits used in the Q-Eye pixel, in the Q-Eye chip itself and in the vision systems developed based on this chip. Also, several examples of chips and systems in operation are presented