Variation Resilient Adaptive Controller for Subthreshold Circuits

Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for power-limited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following novel features: new sensor based on time-to-digital converter for capturing the variations accurately as digital signatures, and an all-digital DC-DC converter incorporating the sensor capable of generating an operating operating Vdd from 0V to 1.2V with a resolution of 18.75mV, suitable for subthreshold circuit operation. The benefits of the proposed controller is reflected with energy improvement of up to 55% compared to when no controller is employed. The detailed implementation and validation of the proposed controller is discussed

Subthreshold circuits: Design, implementation and application

Digital circuits operating in the subthreshold region of the transistor are being used as an ideal option for ultra low power complementary metal-oxide-semiconductor (CMOS) design. The use of subthreshold circuit design in cryptographic systems is gaining importance as a counter measure to power analysis attacks. A power analysis attack is a non-invasive side channel attack in which the power consumption of the cryptographic system can be analyzed to retrieve the encrypted data. A number of techniques to increase the resistance to power attacks have been proposed at algorithmic and hardware levels, but these techniques suffer from large area and power overheads. The main aim of this research is to understand the viability of implementing subthreshold systems for cryptographic applications. Standard cell libraries in subthreshold are designed and a methodology to identify the minimum energy point, aspect ratio, frequency range and operating voltage for CMOS standard cells is defined. As scalar multiplication is the fundamental operation in elliptic curve cryptographic systems, a digit-level gaussian normal basis (GNB) multiplier is implemented using the aforementioned standard cells. A similar standard-cell library is designed for the multiplier to operate in the superthreshold regime. The subthreshold and superthreshold multipliers are then subjected to a differential power analysis attack. Power performance and signal-to-noise ratio (SNR) of both these systems are compared to evaluate the usefulness of the subthreshold design. The power consumption of the subthreshold multiplier is 4.554 uW, the speed of the multiplier is 65.1 KHz and the SNR is 40 dB. The superthreshold multiplier has a power consumption of 4.005 mW, the speed of the multiplier is 330 MHz and the SNR is 200 dB. Reduced power consumption, hence reduced SNR, increases the resistance of the subthreshold multiplier against power analysis attacks. (Refer to PDF for exact formulas)

Analysis and mitigation of variability in subthreshold design

Subthreshold circuit design is a compelling method for ultra-low power applications. However, subthreshold designs show dramati-cally increased sensitivity to process variations due to the exponen-tial relationship of subthreshold drive current with Vth variation. In this paper, we present an analysis of subthreshold energy efficiency considering process variation, and propose methods to mitigate its impact. We show that, unlike superthreshold circuits, random dopant fluctuation is the dominant component of variation in subthreshold operation. We investigate how this variability can be ameliorated with proper circuit sizing and choice of circuit logic depth. We then present a statistical analysis of the energy efficiency of subthreshold circuits considering process variations. We show that the energy optimal supply voltage increases due to process variations and study its dependence on circuit parameters. We verify our analytical mod-els against Monte Carlo SPICE simulations and show that they accu-rately predict the minimum energy and energy optimal supply voltage. Finally, we use the developed statistical energy model to determine the optimal pipelining depth in subthreshold designs

A study on ultra-low power and large-scale design of digital circuit for wireless communications

The continuous growth of recent mobile and portable devices has caused a push greater towards low-power circuit designs. Various methods and techniques have been found, for example, the utilization of concurrent or pipeline architecture with low supply voltage for traditional circuits. Proper designs of subthreshold circuits operating in a weak inversion region achieves ultra-low threshold and supply voltages and has been studied for both analog and digital circuits. The analog circuit has been studied and implemented in many areas such as speech signal and image processing. On the other hand, digital circuits have been studied for very low clock frequency and can be applied in medical devices such as pacemakers and defibrillators. For the idle state of low-power, subthreshold voltage condition has been used for microprocessors in ultra-low voltage operation and leakage current. The idea to study subthreshold operation comes after much research carried out through conventional analysis focusing on, for example, low power, low voltage, low frequency, and application in small circuit systems. Recently, as a result of the aggressive scaling of transistor size for high-performance applications, not only does subthreshold leakage current increase exponentially, but gate leakage and reverse-biased source-substrate and drain-substrate junction band-to-band tunneling (BTBT) currents also increase significantly. The tunneling currents are detrimental to the functionality of the devices. The well-known methods of low-power design (such as voltage scaling, switching activity reduction, architectural techniques of pipelining and parallelism, computer-aided design (CAD) techniques of device sizing, interconnect, and logic optimization). This may not be sufficient in many applications such as portable computing gadgets, and medical electronics, where ultra-low power consumption with medium frequency of operation is the primary requirement. To cope with this, several novel design techniques have been proposed. Energy recovery or adiabatic techniques are promising for reducing power in computation by orders of magnitude. However, they involve the use of high-quality inductors, which makes integration difficult. More recently, the design of digital subthreshold logic was investigated with transistors operated in the subthreshold region. The aim of this study is to achieve ultra-low power communication circuits operating at high frequency. In this situation, we focus on implementing large-scale subthreshold circuits and must explore a new design in which only the CMOS standard cell library is used and simplify the modeling procedure of subthreshold circuits. The conventional design involves subthreshold analysis on a transistor level or cell library preparation under multiple voltage conditions. This procedure has disadvantageous that requires a long time to estimate the circuit performance for operation in the subthreshold region. We proposed scale modeling so we need only to use a typical cell library, which is suitable for large-scale digital circuits such as wireless communication circuits. In the proposed method, each CMOS logic cell operating in the subthreshold region in circuit delays and power dissipation are analyzed and scaled factors are obtained by mapping from typical to subthreshold voltage conditions. This process does not need preparation of a special-purpose CMOS library operating in the sub-threshold region. The critical path delay is also obtained by scaling factors and used for determining the optimal voltage condition that satisfies the required timing constrains. For practical examples, we have designed wireless clrcuits of a channel equalizer, FIR filter and FlT used in an OFDM receiver. These circuits have been power dissipated by adjusting the overall voltage conditions to satisfy the required timing constrains of IEEE802.11a standard. Continuing from the first research, we explore the power reduction on dynamic wordlength and voltage scaling for digital signal processing circuits. The determination of wordlength in digital signal processing (DSP) affects system performance, hardware size, and power consumption. A large wordlength yields better performance in digital hardware but increases power consumption. A small wordlength degrades system performance if the dynamic range is insufficient. Use of a fixed wordlength determined in design-level lacks flexibility for such changeable environments. Use of a dynamic variable wordlength technique can maintain system performance and keep power consumption low by dynamically changing an optimal wordlength for various environments. This technique has been applied to an OFDM demodulator and to an equalizer. There are two ways in reducing power for variable wordlength. One is to decrease switching activities by stopping unnecessary bit operations. Variable wordlength chooses small and large wordlength modes. For a small wordlength mode, unused bits can be masked by zero values. Gated clocks are effective in halting switching activities for registers. However, it requires a clock management in its system. The other is voltage scaling (called as minimum power locus) to normalize a circuit delay for each wordlength mode. A small wordlength has a timing margin in a critical path when the timing delay of a large wordlength is adopted. It enables decreasing a voltage so as to have the same circuit delay of a large wordlength. Thus, dynamic wordlength and voltage scaling (DWVS) is suitable for power reduction in variable wordlength architecture. This second research focus is power modeling for DWVS. The work does transistor-level simulation or actual measurements to analyze power consumption of variable wordlength. However, more rapid analysis and estimation done at gate-level and function-level are required for large scale circuits. We present a new power modeling approach where both voltage scaling and switching activities are modeled as DWVS parameters

Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors.

Temperature sensors are routinely found in devices used to monitor the environment, the human body, industrial equipment, and beyond. In many such applications, the energy available from batteries or the power available from energy harvesters is extremely limited due to limited available volume, and thus the power consumption of sensing should be minimized in order to maximize operational lifetime. Here we present a new method to transduce and digitize temperature at very low power levels. Specifically, two pA current references are generated via small tunneling-current metal-oxide-semiconductor field effect transistors (MOSFETs) that are independent and proportional to temperature, respectively, which are then used to charge digitally-controllable banks of metal-insulator-metal (MIM) capacitors that, via a discrete-time feedback loop that equalizes charging time, digitize temperature directly. The proposed temperature sensor was integrated into a silicon microchip and occupied 0.15 mm2 of area. Four tested microchips were measured to consume only 113 pW with a resolution of 0.21 °C and an inaccuracy of ±1.65 °C, which represents a 628× reduction in power compared to prior-art without a significant reduction in performance

Ultra Low Power Amplification and Digitization System for Neural Signal Recording Applications

The scope is to develop a tunable low power fully integrated bandpass filter and a low power second order sigma-delta ADC modulator for implantable neural signal amplification and digitization applications, with subthreshold circuit design techniques in different CMOS processes. Since biopotentials usually contain low frequency components, the neural filters in this project have to be able to achieve large and predictable time constant for implantable applications. Voltage biased pseudo-resistors are vulnerable to process variations and circuit imperfections, and hence not suitable for implantable applications. A current biased pseudo-resistor is implemented in the neural filters in this work to set the cutoff frequency, and a Taylor series is used to study its linearity. The filters with proposed current biased pseudo-resistors were fabricated in two different CMOS processes and tested. The test results verify that the filters with current biased pseudo-resistors are tunable, and not vulnerable to process variations and circuit imperfections. The filters with current biased pseudo-resistors meet the design requirements of fully integrated, implantable applications. The sigma-delta ADC modulator was designed and simulated in a half micron SOS CMOS process. The simulation results of the ADC confirm the possibility of an ultra low power ADC for neural signal recording applications.School of Electrical & Computer Engineerin

DTMOS-Based 0.4V Ultra Low-Voltage Low-Power VDTA Design and Its Application to EEG Data Processing

In this paper, an ultra low-voltage, ultra low-power voltage differencing transconductance amplifier (VDTA) is proposed. DTMOS (Dynamic Threshold Voltage MOS) transistors are employed in the design to effectively use the ultra low supply voltage. The proposed VDTA is composed of two operational transconductance amplifiers operating in the subthreshold region. Using TSMC 0.18µm process technology parameters with symmetric ±0.2V sup¬ply voltage, the total power consumption of the VDTA block is found as just 5.96 nW when the transconductances have 3.3 kHz, 3 dB bandwidth. The proposed VDTA circuit is then used in a fourth-order double-tuned band-pass filter for processing real EEG data measurements. The filter achieves close to 64 dB dynamic range at 2% THD with a total power consumption of 12.7 nW

Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

Large-capacity Content Addressable Memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more years. This paper provides a new approach towards the design and modeling of Memristor (Memory resistor) based Content Addressable Memory (MCAM) using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture. The non-volatile characteristic and the nanoscale geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures.Comment: 10 pages, 11 figure