CMOS mobility-compensated time reference for crystal replacement

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2015.Apesar da existência de muitas alternativas para geração de base de tempo, não há ainda uma referencia de tempo totalmente integrável que possa oferecer simultaneamente alta precisão, baixa potência e custo de produção reduzido; portanto, não há uma referência de tempo ideal capaz de ter performance melhor do que os osciladores a quartzo disponíveis no mercado. O objetivo principal desse trabalho é de tentar encontrar uma solução em tecnologia CMOS de uma referencia de tempo capaz de substituir osciladores a quartzo na frequência de 32 kHz. Isso implica em projetar um oscilador de baixa potencia, alta precisão e que seja pouco sensível as variações de processo, de tensão e de temperatura. Os elementos básicos do oscilador de relaxação deste trabalho são um transistor zero-Vt que opera como resistor e uma fonte de corrente específica de transistor zero-Vt. Foi desenvolvido também um Schmitt trigger com entrada de corrente e uma fonte de corrente controlada por tensão capaz de acompanhar a variação de corrente devido as variações de processo, tensão e temperatura. As medidas do oscilador fabricados mostraram uma variação de +/- 30ppm/°C na faixa de temperatura de -20°C ate 80°C e uma variação menor do que +/- 500ppm/V para tensão de alimentação entre 0.7 V e 1.8 V. As medidas da estabilidade em frequência mostraram uma variação de +/- 500ppm para estabilidade de longo termo, e um jitter de 2 nano seconds para estabilidade curto termo.Abstract: Despite many alternatives for time generation, no CMOS fully-integrated time reference offers simultaneously high accuracy, low power consumption, and low cost, and, thus, no ideal time reference suitable to replace the xtalclockis available. The main aim of this work is to contribute to find a solution to this problem, which is to realize a low-cost, low-power CMOS time reference circuit that is insensitive to PVT (Process, Voltage, and Temperature) variations. The basic element of the relaxation oscillator is a zero-VtMOSFET that operates as a resistor and a current source which tracks the specific current of the zero-Vt transistor. The design presented here uses acurrent mode Schmitt trigger and a voltage controlled current source, which can track the current variation due to PVT variations. The frequency of oscillation, proportional to the mobility, is compensated by the thermal voltage. The proposed time reference, fabricated in a 180 nm CMOS technology has been designed for 32 kHz. Test and measurement results show a variation of +/- 30ppm/°C from -20°C to 80°C, and less than +/- 500ppm/V for a variation of the supply voltage between 0.7 V to 1.8 V. As regards frequency stability, measurements have shown a variation less than +/- 500ppm for long term stability, and an rms jitter of 2 nanoseconds (66 ppm) for short term stability

Nano-Watt Modular Integrated Circuits for Wireless Neural Interface.

In this work, a nano-watt modular neural interface circuit is proposed for ECoG neuroprosthetics. The main purposes of this work are threefold: (1) optimizing the power-performance of the neural interface circuits based on ECoG signal characteristics, (2) equipping a stimulation capability, and (3) providing a modular system solution to expand functionality. To achieve these aims, the proposed system introduces the following contributions/innovations: (1) power-noise optimization based on the ECoG signal driven analysis, (2) extreme low-power analog front-ends, (3) Manchester clock-edge modulation clock data recovery, (4) power-efficient data compression, (5) integrated stimulator with fully programmable waveform, (6) wireless signal transmission through skin, and (7) modular expandable design. Towards these challenges and contributions, three different ECoG neural interface systems, ENI-1, ENI-16, and ENI-32, have been designed, fabricated, and tested. The first ENI system(ENI-1) is a one-channel analog front-end and fabricated in a 0.25µm CMOS process with chopper stabilized pseudo open-loop preamplifier and area-efficient SAR ADC. The measured channel power, noise and area are 1.68µW at 2.5V power-supply, 1.69µVrms (NEF=2.43), and 0.0694mm^2, respectively. The fabricated IC is packaged with customized miniaturized package. In-vivo human EEG is successfully measured with the fabricated ENI-1-IC. To demonstrate a system expandability and wireless link, ENI-16 IC is fabricated in 0.25µm CMOS process and has sixteen channels with a push-pull preamplifier, asynchronous SAR ADC, and intra-skin communication(ISCOM) which is a new way of transmitting the signal through skin. The measured channel power, noise and area are 780nW, 4.26µVrms (NEF=5.2), and 2.88mm^2, respectively. With the fabricated ENI-16-IC, in-vivo epidural ECoG from monkey is successfully measured. As a closed-loop system, ENI-32 focuses on optimizing the power performance based on a bio-signal property and integrating stimulator. ENI-32 is fabricated in 0.18µm CMOS process and has thirty-two recording channels and four stimulation channels with a cyclic preamplifier, data compression, asymmetric wireless transceiver (Tx/Rx). The measured channel power, noise and area are 140nW (680nW including ISCOM), 3.26µVrms (NEF=1.6), and 5.76mm^2, respectively. The ENI-32 achieves an order of magnitude power reduction while maintaining the system performance. The proposed nano-watt ENI-32 can be the first practical wireless closed-loop solution with a practically miniaturized implantable device.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98064/1/schang_1.pd

Comunicações ópticas por câmera para sistemas de assistência à condução

Communications, whatever its type, is a pillar of our modern society. More specifically, communications by visible light, that show numerous advantages, from electromagnetic spectral efficiency and regulation freedom to energy saving (since it combine illumination and communication). As such, the automotive world is interested in this technology, in particularly, its application into the Intelligent Transport System (ITS). The objective of this work relies on the study and development of a demonstrator able to support VLC communication means in V2V (Vehicle to Vehicle) scenario, making use of the LED luminaries already implemented in nowadays cars. Since the outdoor implementation is one of the requirements, reception based in OCC (Optical Camera Communication) is a viable solution in this conditions. Also the signal processing/decoding is performed by a CNN (Convolutional Neural Network), this type of algorithm shows a huge decoding flexibility and resilience, which benefits the transmission system performance. All the project was done in collaboration with the integrated circuits systems group of Instituto de Telecomunicações de Aveiro and Exatronic Lda company, based in Aveiro and specialized in innovation and investigation (I+I), engineering and manufacturing of electronics.As comunicações, qualquer que seja o seu tipo, mostram-se como um pilar fundamental para a sociedade. Especificamente as comunicações por luz visível, que apresentam inúmeras vantagens, desde a eficiência espectral e mais liberdade de regulamentação, até à energética pois alia duas caracteristicas distintas (iluminação e comunicação) numa só. Como tal, o mundo automóvel apresenta-se como um dos posíveis interessados na aplicação desta tecnologia, mais propriamente a aplicação como parte integrante do sistema inteligente de transportes (ITS). Este trabalho tem como objectivo o estudo e desenvolvimento de um demonstrador capaz de estabelecer um link de comunicação V2V (Vehicle to vehicle) por meio da modulação da luz visivel emitida pelas iluminárias LED já equipadas actualmente nos veículos. Sendo a implementação exterior um dos requerimentos deste sistema, a rececção através de OCC (Optical Camera Communication) mostra-se assim uma solução viável. Assim como o processamento do sinal recebido, que é efectuado por meio de CNNs (Convolutional Neural Networks), que mostram flexibilidade e resiliência, o que benefecia a capacidade do sistema de transmissão. Todo o projecto foi realizado em colaboração com o grupo de circuitos integrados do Instituto de Telecomunicações de Aveiro e a empresa Exatronic Lda, sediada em Aveiro, e especializada em inovação, investigação (I+I), engenharia e produção de eletrónica.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

A Low Temperature Co-fired Ceramic (LTCC) Interposer Based Three-Dimensional Stacked Wire Bondless Power Module

The objective of this dissertation research is to develop a low temperature co-fired ceramic (LTCC) interposer-based module-level 3-D wire bondless stacked power module. As part of the dissertation work, the 3-D wire bondless stack is designed, simulated, fabricated and characterized. The 3-D wire bondless stack is realized with two stand-alone power modules in a half-bridge configuration. Each stand-alone power module consists of two 1200 V 25 A silicon insulated-gate bipolar transistor (IGBT) devices in parallel and two 1200 V 20 A Schottky barrier diodes (SBD) in an antiparallel configuration. A novel interconnection scheme with conductive clamps and a spring loaded LTCC interposer is introduced to establish electrical connection between the stand-alone power modules to connect them in series to realize a half-bridge stack. Process development to fabricate the LTCC based 3-D stack is performed. In traditional power modules, wire bonds are used as a top side interconnections that introduce additional parasitic inductance in the current conduction path and prone to failure mechanism under high thermomechanical stresses. The loop inductance of the proposed 3-D half-bridge module exhibits 71% lower parasitic inductance compared to a wire bonded module. The 3-D stack exhibits better switching performance compared to the wire bonded counterpart. The measurement results for the 3-D stack shows 30% decrease in current overshoot at turn-on and 43% voltage overshoot at turn-off compared to the wire bonded module. Through measurements, it has been shown that the conducted noise reduces by 20 dB in the frequency range 20-30 MHz for the 3-D stack compared to the wire bonded counterpart. A simulation methodology using co-simulation techniques using ANSYS EM software tools is developed to predict EMI of a power module. Hardware verification of the proposed simulation methodology is performed to validate the co-simulation technique. The correlation coefficient between the measurement and simulation is found to be 0.73. It is shown that 53% of the variability in the simulation can be explained by the simulated result. Moreover, the simulated and measured amplitudes of the EMI spectrum closely match with each other with some variations due to round-off errors due to the FFT conversion

Accurate CMOS compact model and the corresponding circuit simulation in the presence of statistical variability and ageing

As CMOS scales down to sub-50 nm, it faces critical dimensions of charge and matter granularities, leading to the drastic increase of device parameter dispersion, named statistical variability, which is one of the main contemporary challenges for further downscaling and makes each device atomistically different leading to broad dispersion of their electrical characteristics. In addition, device reliability concerns gain inertia; among them Bias Temperature Instability (BTI) shortens device lifetime by trapping charges in defect states of the insulator or at the interface. The interplay between statistical variability and BTI results in more variations on device performance and thus greatly affect circuit performance. In turn design methodologies must evolve towards variability and reliability aware design. To do so statistical compact models including both the effects of statistical variability and BTI-induced ageing are required for the large-scale statistical circuit simulation of variability and reliability. In this study, the application of accurate compact models, that describe performance variation in the presence of both statistical variability and reliability at arbitrary BTI-induced ageing levels, to SRAM circuit simulation is described. Both SRAM cell stability and write performance are evaluated and it is seen that, due to the accurate description of device performance distributions provided by the compact models and the sensitivity of these SRAM performance metrics on device performance, the approach presented here is better suited to high-sigma statistical circuit analysis than conventional approaches based upon assumed Gaussian distributions. The approach is demonstrated using a 25 nm gate length bulk MOSFET whose performance variation is obtained from statistical TCAD simulation using the GSS simulator GARAND. The simulated performance data is then used directly as the target for BSIM4 compact model extraction that ensures device figures of merit are well resolved for each device in a statistical ensemble. The distribution of compact model parameters is then generalised into an algebraic form using Generalized Lambda Distribution (GLD) methods, so that a sufficiently large number of compact models can later be generated and interpolated at arbitrary ageing levels. Finally compact models generated in this way are used to evaluate SRAM write performance and stability under the influence of statistical variability and BTI-induced ageing

Robust low power CMOS methodologies for ISFETs instrumentation

I have developed a robust design methodology in a 0.18 [Mu]m commercial CMOS process to circumvent the performance issues of the integrated Ions Sensitive Field Effect Transistor (ISFET) for pH detection. In circuit design, I have developed frequency domain signal processing, which transforms pH information into a frequency modulated signal. The frequency modulated signal is subsequently digitized and encoded into a bit-stream of data. The architecture of the instrumentation system consists of a) A novel front-end averaging amplifier to interface an array of ISFETs for converting pH into a voltage signal, b) A high linear voltage controlled oscillator for converting the voltage signal into a frequency modulated signal, and c) Digital gates for digitizing and differentiating the frequency modulated signal into an output bit-stream. The output bit stream is indistinguishable to a 1st order sigma delta modulation, whose noise floor is shaped by +20dB/decade. The fabricated instrumentation system has a dimension of 1565 [Mu] m 1565 [Mu] m. The chip responds linearly to the pH in a chemical solution and produces a digital output, with up to an 8-bit accuracy. Most importantly, the fabricated chips do not need any post-CMOS processing for neutralizing any trapped-charged effect, which can modulate on-chip ISFETs’ threshold voltages into atypical values. As compared to other ISFET-related works in the literature, the instrumentation system proposed in this thesis can cope with the mismatched ISFETs on chip for analogue-to-digital conversions. The design methodology is thus very accurate and robust for chemical sensing

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields