Characterisation of thermal and coupling effects in advanced silicon MOSFETs

PhD ThesisNew approaches to metal-oxide-semiconductor field effect transistor (MOSFET) engineering emerge in order to keep up with the electronics market demands. Two main candidates for the next few generations of Moore’s law are planar ultra-thin body and buried oxide (UTBB) devices and three-dimensional FinFETs. Due to miniature dimensions and new materials with low thermal conductivity, performance of advanced MOSFETs is affected by self-heating and substrate effects. Self-heating results in an increase of the device temperature which causes mobility reduction, compromised reliability and signal delays. The substrate effect is a parasitic source and drain coupling which leads to frequency-dependent analogue behaviour. Both effects manifest themselves in the output conductance variation with frequency and impact analogue as well as digital performance. In this thesis self-heating and substrate effects in FinFETs and UTBB devices are characterised, discussed and compared. The results are used to identify trade-offs in device performance, geometry and thermal properties. Methods how to optimise the device geometry or biasing conditions in order to minimise the parasitic effects are suggested. To identify the most suitable technique for self-heating characterisation in advanced semiconductor devices, different methods of thermal characterisation (time and frequency domain) were experimentally compared and evaluated alongside an analytical model. RF and two different pulsed I-V techniques were initially applied to partially depleted silicon-on-insulator (PDSOI) devices. The pulsed I-V hot chuck method showed good agreement with the RF technique in the PDSOI devices. However, subsequent analysis demonstrated that for more advanced technologies the time domain methods can underestimate self-heating. This is due to the reduction of the thermal time constants into the nanosecond range and limitations of the pulsed I-V set-up. The reduction is related to the major increase of the surface to volume ratio in advanced MOSFETs. Consequently the work showed that the thermal properties of advanced semiconductor devices must be characterised within the frequency domain. For UTBB devices with 7-8 nm Si body and 10 nm ultra-thin buried oxide (BOX) the analogue performance degradation caused by the substrate effects can be stronger than the analogue performance degradation caused by self-heating. However, the substrate effects can be effectively reduced if the substrate doping beneath the buried ii oxide is adjusted using a ground plane. In the MHz – GHz frequency range the intrinsic voltage gain variation is reduced ~6 times when a device is biased in saturation if a ground plane is implemented compared with a device without a ground plane. UTBB devices with 25 nm BOX were compared with UTBB devices with 10 nm BOX. It was found that the buried oxide thinning from 25 nm to 10 nm is not critical from the thermal point of view as other heat evacuation paths (e.g. source and drain) start to play a role. Thermal and substrate effects in FinFETs were also analysed. It was experimentally shown that FinFET thermal properties depend on the device geometry. The thermal resistance of FinFETs strongly varies with the fin width and number of parallel fins, whereas the fin spacing is less critical. The results suggest that there are trade-offs between thermal properties and integration density, electrostatic control and design complexity, since these aspects depend on device geometry. The high frequency substrate effects were found to be effectively reduced in devices with sub-100 nm wide fins.Engineering and Physical Sciences Research Council (EPSRC) and EU fundin

The effects of process variations on performance and robustness of bulk CMOS and SOI implementations of C-elements

Advances in semiconductor technology have been driven by the continuous demands of market forces for IC products with higher performance and greater functionality per unit area. To date industry has addressed these demands, principally, by scaling down device dimensions. However, several unintended consequences have undermined the benefits obtained from the advances in technology, firstly, the growing impact of process variations on interconnectivity delay, aggravated by the increase in the amount of interconnectivity as circuit complexity increases. Overall, the difficulty of establishing delay parameters in a circuit is adversely impacting on the attainment of the timing closure for a design. Secondly, the increase in the susceptibility of the circuits , even at ground level, to the effects of soft errors due to the reduction in supply voltages and nodal capacitances, together with the increase in the number of nodes in a circuit as the functionality per unit area increases. The aim of this research has been to model and analyse the reliability of logic circuits with regard to the impact of process variations and soft errors, and to finds ways to minimise these effects using different process technologies such as fully depleted silicon on insulator (FDSOI) and partially depleted silicon on insulator (PDSOI) technologies, together with the implementation of different circuit architectures. In view of the increased susceptibility of logic elements to the effects of process variations and soft errors as device geometries are reduced, a logic element which is not only widely used but also typical to asynchronous design is the Muller C-element, which can be realised in a number of different circuit configurations. The robustness of various C-element configurations implemented in different technologies with regard to the effects of process variations and soft errors was examined using the design of the experiment (DoE) and response surface (RSM) techniques. It was found that the circuits based on SOI technology were more robust compared with bulk silicon technology. On the other hand, from the circuit architecture perspective, the differential logic implementations of C-element were found to be more resilient to the effects of process variation and soft errors in comparison with the other C-element implementations investigated.EThOS - Electronic Theses Online ServiceMutah UniversityGBUnited Kingdo

The effects of process variations on performance and robustness of bulk CMOS and SOI implementations of C-elements

Advances in semiconductor technology have been driven by the continuous demands of market forces for IC products with higher performance and greater functionality per unit area. To date industry has addressed these demands, principally, by scaling down device dimensions. However, several unintended consequences have undermined the benefits obtained from the advances in technology, firstly, the growing impact of process variations on interconnectivity delay, aggravated by the increase in the amount of interconnectivity as circuit complexity increases. Overall, the difficulty of establishing delay parameters in a circuit is adversely impacting on the attainment of the timing closure for a design. Secondly, the increase in the susceptibility of the circuits , even at ground level, to the effects of soft errors due to the reduction in supply voltages and nodal capacitances, together with the increase in the number of nodes in a circuit as the functionality per unit area increases. The aim of this research has been to model and analyse the reliability of logic circuits with regard to the impact of process variations and soft errors, and to finds ways to minimise these effects using different process technologies such as fully depleted silicon on insulator (FDSOI) and partially depleted silicon on insulator (PDSOI) technologies, together with the implementation of different circuit architectures. In view of the increased susceptibility of logic elements to the effects of process variations and soft errors as device geometries are reduced, a logic element which is not only widely used but also typical to asynchronous design is the Muller C-element, which can be realised in a number of different circuit configurations. The robustness of various C-element configurations implemented in different technologies with regard to the effects of process variations and soft errors was examined using the design of the experiment (DoE) and response surface (RSM) techniques. It was found that the circuits based on SOI technology were more robust compared with bulk silicon technology. On the other hand, from the circuit architecture perspective, the differential logic implementations of C-element were found to be more resilient to the effects of process variation and soft errors in comparison with the other C-element implementations investigated.EThOS - Electronic Theses Online ServiceMutah UniversityGBUnited Kingdo

Reliability Investigations of MOSFETs using RF Small Signal Characterization

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliograph

Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA

IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications. Not all the devices will require of high performance but will require of low power hungry systems since most of them will be powered with a battery. Conventional CMOS technologies cannot cover these needs even scaling it to very small regimes, which appear other problems. Hence, new technologies are emerging to cover the needs of this devices. One promising technology is the UTBB FDSOI, which achieves good performance with very good energy efficiency. This project characterizes this technology to obtain a set of parameters of interest for analog/RF design. Finally, with the help of a low-power design methodology (gm/Id approach), a design of an ULP ULV LNA is performed to check the suitability of this technology for IoT

Analyse et modélisation des phénomènes de mismatch des transistors MOSFET avancées

For correct operation, certain analog and digital circuits, such as current mirrors or SRAM, require pairs of MOS transistors that are electrically identical. Real devices, however, suffer from random local variations in the electrical parameters, a problem referred to as mismatch. The aim of this thesis is to understand the physical causes of mismatch, to quantify this phenomenon, and to propose solutions that enable to reduce its effects. In this context, four major areas are treated. The first one focuses on the optimization of mismatch measurement methodologies. A new technique for the measurement of Vt and β mismatch and an ID mismatch model are proposed, analyzed and applied to experimental data for 28 nm Bulk and FD SOI technologies. The second area focuses on the characterization of different configurations of MOS transistors in order to propose design architectures that are optimized for certain applications. Specifically, the possibility of replacing LDEMOS with transistors in cascode configuration is analyzed. The third area focuses on the analysis and modeling of mismatch phenomena in advanced Bulk and SOI transistors. Three aspects are analyzed: 1) the impact of the introduction of germanium in P channel of 28nm BULK transistors; 2) the elimination of the metal gate contribution to Vt mismatch by using 20nm Gate-last Bulk technology; 3) a descriptive study of the principal contributions to Vt, β and ID mismatch in 28 and 14 nm FD SOI technologies. The last area treats the mismatch trends with transistor aging. NBTI stress tests were applied to PMOS 28nm FD SOI transistors. Models of the Vt and β mismatch trends as a function of the induced interface traps and fixed charges at the Si/SiO2 interface and in the oxide were developed and discussed.Afin de réaliser correctement leur fonction, certains blocs analogiques ou numériques comme les miroirs de courant ou les SRAM, nécessitent des paires de transistors MOS électriquement identiques. Cependant, les dispositifs sur silicium, même appariés, subissent des variations locales aléatoires ce qui fait varier leurs performances électriques. Ce phénomène est connu sous le nom désappariement. L'objectif de cette thèse est de comprendre les causes physiques de ce désappariement, de le quantifier et de proposer des solutions pour le réduire. Dans ce contexte, quatre thèmes principaux sont développés. Le premier thème se focalise sur l'optimisation des méthodologies de mesures des phénomènes de désappariement. Une nouvelle méthode de mesure du désappariement de Vt et de β ainsi qu'un nouveau modèle de désappariement de ID sont proposés, analysés et appliqués à des données mesurées sur des technologies 28nm Bulk et FD SOI. Le second thème se concentre sur la caractérisation des différentes configurations de transistor MOS afin de proposer l'architecture optimale en fonction des applications visées. Ainsi, la possibilité de remplacer le LDEMOS par une configuration cascode est analysée en détail. Le troisième thème se focalise sur l'analyse et la modélisation des phénomènes de désappariement des transistors MOS avancés. Trois aspects sont analysés : 1) l'introduction du Ge dans le canal P des technologies 28nm BULK, 2) la suppression de la contribution de la grille sur le désappariement de Vt en utilisant la technologie 20 nm métal-Gate-Last 3) un descriptif des principaux contributeurs au désappariement de Vt, β et ID dans les technologies 28 et 14nm FD SOI. Le dernier thème traite du comportement du désappariement des transistors MOS après vieillissement. Un vieillissement NBTI a été appliqué sur des PMOS de la technologie 28nm FD SOI. Des modèles de comportement de Vt et de β en fonction du nombre de charges fixes ou d'états d'interfaces induits à l'interface Si/SiO2 ou dans l'oxyde sont proposés et analysés

Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference

MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR

As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET

Développement de modèles pour l'évaluation des performances circuit des technologies CMOS avancées sub-20nm

Depuis la commercialisation du premier circuit intégré en 1971, l'industrie de la microélectronique s'est fixée comme leitmotiv de réduire les dimensions des transistors MOSFETs, en suivant la loi de Moore. Comme indiqué par Dennard, cette miniaturisation améliore automatiquement les performances des transistors. A partir des nœuds 28-22nm, les effets canaux courts sont trop difficiles à contrôler et de nouvelles architectures de transistors sont introduites: FDSOI pour STMicroelectronics, Trigate pour Intel. Dans ce contexte, l'évaluation des performances des technologies CMOS est clé et les travaux de cette thèse proposent de les évaluer au niveau circuit. Des modèles spécifiques d'estimation des paramètres électrostatiques et des capacités parasites sont développés. Ceux-ci sont d'abord utilisés sur des technologies amonts (co-intégration III-V/Ge et intégration 3D) puis sont implémentés en VerilogA pour être utilisés avec les outils conventionnel de CAO. Ceci fournit un modèle compact prédictif et utilisable pour toutes les architectures CMOS, qui est utilisé pour évaluer les performances logiques et SRAM des architectures BULK, FDSOI et Trigate aux nœuds 20nm et 16nm.Since the commercialization of the first integrated circuit in 1971, the microelectronic industry has fixed as an objective to reduce MOSFET transistor dimensions, following Moore's law. As indicated by Dennard, this miniaturization automatically improves device performances. Starting from the 28-22nm technological nodes, short channel effects are to strong and industrial companies choose to introduce new device structure: FDSOI for STMicroelectronics and Trigate for Intel. In such a context, CMOS technology performance evaluation is key and this thesis proposes to evaluate them at circuit level. Specific models for electrostatic parameters and parasitic capacitances for each device structure are developed for each device structure. Those models have first been used to evaluate performances of advanced technologies, such as III-V/Ge co-integration and 3D monolithic integration and have then been implemented in VerilogA to ensure compatibility with conventional CAD tools such as ELDO. This provides a compact model, predictive and usable for each device structure, which has been used to evaluated logic and SRAM performances of BULK, FDSOI and Trigate devices for the 20nm and 16nm technology node.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF