Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter

We study, using numerical simulation, the intrinsic parameter fluctuations in sub 10 nm gate length double gate MOSFETs introduced by discreteness of charge and atomicity of matter. The employed "atomistic" drift-diffusion simulation approach includes quantum corrections based on the density gradient formalism. The quantum confinement and source-to-drain tunnelling effects are carefully calibrated in respect of self-consistent Poisson-Schrodinger and nonequilibrium Green's function simulations. Various sources of intrinsic parameter fluctuations, including random discrete dopants in the source/drain regions, single dopant or charged defect state in the channel region and gate line edge roughness, are studied in detail

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed

Theoretical Engineering and Satellite Comlink of a PTVD-SHAM System

This paper focuses on super helical memory system's design, 'Engineering, Architectural and Satellite Communications' as a theoretical approach of an invention-model to 'store time-data'. The current release entails three concepts: 1- an in-depth theoretical physics engineering of the chip including its, 2- architectural concept based on VLSI methods, and 3- the time-data versus data-time algorithm. The 'Parallel Time Varying & Data Super-helical Access Memory' (PTVD-SHAM), possesses a waterfall effect in its architecture dealing with the process of voltage output-switch into diverse logic and quantum states described as 'Boolean logic & image-logic', respectively. Quantum dot computational methods are explained by utilizing coiled carbon nanotubes (CCNTs) and CNT field effect transistors (CNFETs) in the chip's architecture. Quantum confinement, categorized quantum well substrate, and B-field flux involvements are discussed in theory. Multi-access of coherent sequences of 'qubit addressing' in any magnitude, gained as pre-defined, here e.g., the 'big O notation' asymptotically confined into singularity while possessing a magnitude of 'infinity' for the orientation of array displacement. Gaussian curvature of k(k<0) is debated in aim of specifying the 2D electron gas characteristics, data storage system for defining short and long time cycles for different CCNT diameters where space-time continuum is folded by chance for the particle. Precise pre/post data timing for, e.g., seismic waves before earthquake mantle-reach event occurrence, including time varying self-clocking devices in diverse geographic locations for radar systems is illustrated in the Subsections of the paper. The theoretical fabrication process, electromigration between chip's components is discussed as well.Comment: 50 pages, 10 figures (3 multi-figures), 2 tables. v.1: 1 postulate entailing hypothetical ideas, design and model on future technological advances of PTVD-SHAM. The results of the previous paper [arXiv:0707.1151v6], are extended in order to prove some introductory conjectures in theoretical engineering advanced to architectural analysi

Gunn Effect in Silicon Nanowires: Charge Transport under High Electric Field

Gunn (or Gunn-Hilsum) Effect and its associated negative differential resistivity (NDR) emanates from transfer of electrons between two different energy bands in a semiconductor. If applying a voltage (electric field) transfers electrons from an energy sub band of a low effective mass to a second one with higher effective mass, then the current drops. This manifests itself as a negative slope or NDR in the I-V characteristics of the device which is in essence due to the reduction of electron mobility. Recalling that mobility is inversely proportional to electron effective mass or curvature of the energy sub band. This effect was observed in semiconductors like GaAs which has direct bandgap of very low effective mass and its second indirect sub band is about 300 meV above the former. More importantly a self-repeating oscillation of spatially accumulated charge carriers along the transport direction occurs which is the artifact of NDR, a process which is called Gunn oscillation and was observed by J. B. Gunn. In sharp contrast to GaAs, bulk silicon has a very high energy spacing (~1 eV) which renders the initiation of transfer-induced NDR unobservable. Using Density Functional Theory (DFT), semi-empirical 10 orbital ($sp^{3}d^{5}s^{*}$) Tight Binding (TB) method and Ensemble Monte Carlo (EMC) simulations we show for the first time that (a) Gunn Effect can be induced in narrow silicon nanowires with diameters of 3.1 nm under 3 % tensile strain and an electric field of 5000 V/cm, (b) the onset of NDR in I-V characteristics is reversibly adjustable by strain and (c) strain can modulate the value of resistivity by a factor 2.3 for SiNWs of normal I-V characteristics i.e. those without NDR. These observations are promising for applications of SiNWs in electromechanical sensors and adjustable microwave oscillators.Comment: 18 pages, 6 figures, 63 reference

Spatially controlled electrostatic doping in graphene p-i-n junction for hybrid silicon photodiode

Sufficiently large depletion region for photocarrier generation and separation is a key factor for two-dimensional material optoelectronic devices, but few device configurations has been explored for a deterministic control of a space charge region area in graphene with convincing scalability. Here we investigate a graphene-silicon p-i-n photodiode defined in a foundry processed planar photonic crystal waveguide structure, achieving visible - near-infrared, zero-bias and ultrafast photodetection. Graphene is electrically contacting to the wide intrinsic region of silicon and extended to the p an n doped region, functioning as the primary photocarrier conducting channel for electronic gain. Graphene significantly improves the device speed through ultrafast out-of-plane interfacial carrier transfer and the following in-plane built-in electric field assisted carrier collection. More than 50 dB converted signal-to-noise ratio at 40 GHz has been demonstrated under zero bias voltage, with quantum efficiency could be further amplified by hot carrier gain on graphene-i Si interface and avalanche process on graphene-doped Si interface. With the device architecture fully defined by nanomanufactured substrate, this study is the first demonstration of post-fabrication-free two-dimensional material active silicon photonic devices.Comment: NPJ 2D materials and applications (2018

Modeling Emerging Semiconductor Devices for Circuit Simulation

Circuit simulation is an indispensable part of modern IC design. The significant cost of fabrication has driven researchers to verify the chip functionality through simulation before submitting the design for final fabrication. With the impending end of Moore’s Law, researchers all over the world are looking for new devices with enhanced functionality. A plethora of promising emerging devices has been proposed in recent years. In order to leverage the full potential of such devices, circuit designers need fast, reliable models for SPICE simulation to explore different applications. Most of these new devices have complex underlying physical mechanism rendering the model development an extremely challenging task. For the models to be of practical use, they have to enable fast and accurate simulation that rules out the possibility of numerically solving a system of partial differential equations to arrive at a solution. In this chapter, we show how different modeling approaches can be used to simulate three emerging semiconductor devices namely, silicon- on- insulator four gate transistor(G4FET), perimeter gated single photon avalanche diode (PG-SPAD) and insulator-metal transistor (IMT) device with volatile memristance. All the models have been verified against experimental /TCAD data and implemented in commercial circuit simulator

Compact electrothermal reliability modeling and experimental characterization of bipolar latchup in SiC and CoolMOS power MOSFETs

In this paper, a compact dynamic and fully coupled electrothermal model for parasitic BJT latchup is presented and validated by measurements. The model can be used to enhance the reliability of the latest generation of commercially available power devices. BJT latchup can be triggered by body-diode reverse-recovery hard commutation with high dV/dt or from avalanche conduction during unclamped inductive switching. In the case of body-diode reverse recovery, the base current that initiates BJT latchup is calculated from the solution of the ambipolar diffusion equation describing the minority carrier distribution in the antiparallel p-i-n body diode. For hard commutation with high dV/dt, the displacement current of the drain-body charging capacitance is critical for BJT latchup, whereas for avalanche conduction, the base current is calculated from impact ionization. The parasitic BJT is implemented in Simulink using the Ebers-Moll model and the temperature is calculated using a thermal network matched to the transient thermal impedance characteristic of the devices. This model has been applied to CoolMOS and SiC MOSFETs. Measurements show that the model correctly predicts BJT latchup during reverse recovery as a function of forward-current density and temperature. The model presented, when calibrated correctly by device manufacturers and applications engineers, is capable of benchmarking the robustness of power MOSFETs