Simulation of FinFET Structures

The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications

Silicon Nanowire Based Photodetectors: Modeling and Fabrication

This research is focused on investigating the role of silicon nanowires in designing high gain, high sensitivity photodetectors, and is based on both device modeling and fabrication. We demonstrate that the superior electrostatic control within the nanowires enables us to effectively engineer the energy band and design novel photodetector architectures. This is due to the high surface to volume ratio in nanowires which allows for the ability to change the electrical properties of a nanowire device in response to a voltage applied to the gate contact. In the first part of the thesis, two photodetector geometries are proposed and theoretically studied. The first geometry is a Metal Oxide Semiconductor (MOS) device with nanowires incorporated in its channel. The next geometry is a junction-less phototransistor, e.g. a photoconductor with a third terminal as the gate. Both geometries are important due to their ability to generate optical gain. For both cases, first the role of nanowire parameters and their pros and cons on the device photo-response is investigated. Afterwards, we propose modifications to the device geometry in order to improve the performance of the device in terms of optical gain and sensitivity. The first modification is allocating a wide region for light absorption in the channel, since single nanowire based photodetectors suffer from lack of efficient absorption, due to their small cross sectional area. Use of phototransistors also helps the photo-current increase, due to the device's internal gain. The second modification incorporates two nanowire/ gate geometries to improve the device photo-response, in terms of both dark- and photo-current. The charge flow in each nanowire is controlled by a gate, which changes the energy band within the nanowire. This band engineering allows for both increasing the optical gain of the phototransistor, and keeping the dark current low. We report nanowire based phototransistors that are potentially able to detect low levels of light intensity (photon rate of less than 50/s). The second part of the thesis is devoted to the fabrication of the nanowire based structures. Top-down approach is used, mainly due to the better control on the nanowire size and position, and repeatability of the processes involved. Fabrication process includes several steps of electron beam lithography, dry and wet etching, metal and dielectric deposition and annealing. Pre-developed recipes are used when available. New recipes are also developed to better suit the specific needs of the devices. The measurement results of the fabricated structures verify most of the concepts proposed in the modeling phase. In the third part of this thesis, we characterize MOS capacitors with and without illumination, based on Silicon on Insulator (SOI) structures used in the previous chapters. Here, we report the first observation of photon induced negative capacitance in a conventional Metal Oxide Semiconductor (MOS) capacitor without the use of ferroelectric materials. Design and implementation of this phenomenon is presented in a capacitor where an aluminum oxide layer serves as the gate dielectric, and the capacitor is in depletion mode. Through extensive modeling, we establish that trap states at the semiconductor-oxide interface, coupled with the injection of photo-generated electrons are responsible for the negative capacitance. We find that varying the trap density and/or light intensity can tune the value of the negative capacitance. We show that in the presence of photons, the experimentally measured quasi-static capacitance in depletion is almost twice the value without photons. Further, the measured capacitance is larger than the values in accumulation and inversion.1 yea

Reliability Investigations of MOSFETs using RF Small Signal Characterization

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliograph

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

III-V Nanowire MOSFET High-Frequency Technology Platform

This thesis addresses the main challenges in using III-V nanowireMOSFETs for high-frequency applications by building a III-Vvertical nanowire MOSFET technology library. The initial devicelayout is designed, based on the assessment of the current III-V verticalnanowire MOSFET with state-of-the-art performance. The layout providesan option to scale device dimensions for the purpose of designing varioushigh-frequency circuits. The nanowire MOSFET device is described using1D transport theory, and modeled with a compact virtual source model.Device assessment is performed at high frequencies, where sidewall spaceroverlaps have been identified and mitigated in subsequent design iterations.In the final stage of the design, the device is simulated with fT > 500 GHz,and fmax > 700 GHz.Alongside the III-V vertical nanowire device technology platform, adedicated and adopted RF and mm-wave back-end-of-line (BEOL) hasbeen developed. Investigation into the transmission line parameters revealsa line attenuation of 0.5 dB/mm at 50 GHz, corresponding to state-ofthe-art values in many mm-wave integrated circuit technologies. Severalkey passive components have been characterized and modeled. The deviceinterface module - an interconnect via stack, is one of the prominentcomponents. Additionally, the approach is used to integrate ferroelectricMOS capacitors, in a unique setting where their ferroelectric behavior iscaptured at RF and mm-wave frequencies.Finally, circuits have been designed. A proof-of-concept circuit, designedand fabricated with III-V lateral nanowire MOSFETs and mm-wave BEOL, validates the accuracy of the BEOL models, and the circuit design. Thedevice scaling is shown to be reflected into circuit performance, in aunique device characterization through an amplifier noise-matched inputstage. Furthermore, vertical-nanowire-MOSFET-based circuits have beendesigned with passive feedback components that resonate with the devicegate-drain capacitance. The concept enables for device unilateralizationand gain boosting. The designed low-noise amplifiers have matching pointsindependent on the MOSFET gate length, based on capacitance balancebetween the intrinsic and extrinsic capacitance contributions, in a verticalgeometry. The proposed technology platform offers flexibility in device andcircuit design and provides novel III-V vertical nanowire MOSFET devicesand circuits as a viable option to future wireless communication systems

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Modeling Of Two Dimensional Graphene And Non-graphene Material Based Tunnel Field Effect Transistors For Integrated Circuit Design

The Moore’s law of scaling of metal oxide semiconductor field effect transistor (MOSFET) had been a driving force toward the unprecedented advancement in development of integrated circuit over the last five decades. As the technology scales down to 7 nm node and below following the Moore’s law, conventional MOSFETs are becoming more vulnerable to extremely high off-state leakage current exhibiting a tremendous amount of standby power dissipation. Moreover, the fundamental physical limit of MOSFET of 60 mV/decade subthreshold slope exacerbates the situation further requiring current transport mechanism other than drift and diffusion for the operation of transistors. One way to limit such unrestrained amount of power dissipation is to explore novel materials with superior thermal and electrical properties compared to traditional bulk materials. On the other hand, energy efficient steep subthreshold slope devices are the other possible alternatives to conventional MOSFET based on emerging novel materials. This dissertation addresses the potential of both advanced materials and devices for development of next generation energy efficient integrated circuits. Among the different steep subthreshold slope devices, tunnel field effect transistor (TFET) has been considered as a promising candidate after MOSFET. A superior gate control on source-channel band-to-band tunneling providing subthreshold slopes well below than 60 mV/decade. With the emergence of atomically thin two-dimensional (2D) materials, interest in the design of TFET based on such novel 2D materials has also grown significantly. Graphene being the first and the most studied among 2D materials with exotic electronic and thermal properties. This dissertation primarily considers current transport modeling of graphene based tunnel devices from transport phenomena to energy efficient integrated circuit design. Three current transport models: semi-classical, semi-quantum and numerical simulations are described for the modeling of graphene nanoribbon tunnel field effect transistor (GNR TFET) where the semi-classical model is in close agreement with the quantum transport simulation. Moreover, the models produced are also extended for integrated circuit design using Verilog-A hardware description language for logic design. In order to overcome the challenges associated with the band gap engineering for making graphene transistor for logic operation, the promise of graphene based interlayer tunneling transistors are discussed along with their existing fundamental physical limitation of subthreshold slope. It has been found that such interlayer tunnel transistor has very poor electrostatic gate control on drain current. It gives subthreshold slope greater than the thermionic limit of 60 mV/decade at room temperature. In order to resolve such limitation of interlayer tunneling transistors, a new type of transistor named “junctionless tunnel effect transistor (JTET)” has been invented and modeled for the first time considering graphene-boron nitride (BN)-graphene and molybdenum disulfide (MoS2)-boron nitride (BN) heterostructures, where the interlayer tunneling mechanism controls the source-drain ballistic transport instead of depleting carriers in the channel. Steep subthreshold slope, low power and high frequency THz operation are few of the promising features studied for such graphene and MoS2 JTETs. From current transport modeling to energy efficient integrated circuit design using Verilog-A has been carried out for these new devices as well. Thus, findings in this dissertation would suggest the exciting opportunity of a new class of next generation energy efficient material based transistors as switches

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

By the continuing downscaling of sub-micron transistors in the range of few to one deca-nanometers, we focus on the increasing relative level of the low-frequency noise in these devices. Large amount of published data and models are reviewed and summarized, in order to capture the state-of-the-art, and to observe that the 1/area scaling of low-frequency noise holds even for carbon nanotube devices, but the noise becomes too large in order to have fully deterministic devices with area less than 10nm×10nm. The low-frequency noise models are discussed from the point of view that the noise can be both intrinsic and coupled to the charge transport in the devices, which provided a coherent picture, and more interestingly, showed that the models converge each to other, despite the many issues that one can find for the physical origin of each model. Several derivations are made to explain crossovers in noise spectra, variable random telegraph amplitudes, duality between energy and distance of charge traps, behaviors and trends for figures of merit by device downscaling, practical constraints for micropower amplifiers and dependence of phase noise on the harmonics in the oscillation signal, uncertainty and techniques of averaging by noise characterization. We have also shown how the unavoidable statistical variations by fabrication is embedded in the devices as a spatial “frozen noise”, which also follows 1/area scaling law and limits the production yield, from one side, and from other side, the “frozen noise” contributes generically to temporal 1/f noise by randomly probing the embedded variations during device operation, owing to the purely statistical accumulation of variance that follows from cause-consequence principle, and irrespectively of the actual physical process. The accumulation of variance is known as statistics of “innovation variance”, which explains the nearly log-normal distributions in the values for low-frequency noise parameters gathered from different devices, bias and other conditions, thus, the origin of geometric averaging in low-frequency noise characterizations. At present, the many models generally coincide each with other, and what makes the difference, are the values, which, however, scatter prominently in nanodevices. Perhaps, one should make some changes in the approach to the low-frequency noise in electronic devices, to emphasize the “statistics behind the numbers”, because the general physical assumptions in each model always fail at some point by the device downscaling, but irrespectively of that, the statistics works, since the low-frequency noise scales consistently with the 1/area law

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization