Depletion isolation effect in Vertical MOSFETS during transition from partial to fully depleted operation

A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200–60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain–current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60–10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate–gate coupling contribute to the drain–current for pillar thicknesses between 100–40 nm

DOWNSCALING OF 0.25uM TO O.13uM NMOS USING SILVACO SOFTWARE WITH DIFFERENT SUBMICRON TECHNOLOGY

For the last three decades, MOS device technologies have been improved due to downscaling. It consumes less power, have shorter delay and occupy less space. The CMOS comprises of p-type and n-type, has become the main growth of miniaturization microelectronics industry. In this project, ATHENA andATLAS are simulators used with the objective to downscale 0.25um to 0.13um NMOS using two different recipes and to obtain its electrical characteristic. Ascaling factor, a of 1.923 is utilized. Three factors are investigated; the gate length (Lg), gate oxide thickness (U) and threshold voltage (Vth) adjust implant. The parameters evaluated include W, Vth and saturation current (WO as well as ID-VD, Id-Vg and subthreshold current (St) curve. After downscaling to 0.13um, both recipes haveWvalues of3.36nm while the Vth obtain are 0.31V and 0.37V respectively. The W value is 343uA/um and 519uA/um while the St is 65mV/dec and 128mV/dec respectively. Each recipe has its own drawback. First recipe has lower Id^ and lower St while second recipe has higher IDsat and higher St Higher W means the device can perform at taster speed while lower St. shows the device has good turn-off characteristics. Overall, the electrical parameters obtained are agreeable with ITRS requirement and other reported works except for the result ofW This could be due to the direct scaling. Other parameters such as St could not be compared as itis confidential to the public

DOWNSCALING OF 0.25|iM TO O.ttpM NMOS USING SILVACO SOFTWARE WITH DIFFERENT SUBMICRON TECHNOLOGY

For the last three decades, MOS device technologies have been improved due to downscaling. It consumes less power, have shorter delay and occupy less space. The CMOS comprises of p-type and n-type, has become the main growth of miniaturization microelectronics industry. In this project, ATHENA andATLAS are simulators used with the objective to downscale 0.25um to 0.13um NMOS using two different recipes and to obtain its electrical characteristic. Ascaling factor, a of 1.923 is utilized. Three factors are investigated; the gate length (Lg), gate oxide thickness (U) and threshold voltage (Vth) adjust implant. The parameters evaluated include W, Vth and saturation current (WO as well as ID-VD, Id-Vg and subthreshold current (St) curve. After downscaling to 0.13um, both recipes haveWvalues of3.36nm while the Vth obtain are 0.31V and 0.37V respectively. The W value is 343uA/um and 519uA/um while the St is 65mV/dec and 128mV/dec respectively. Each recipe has its own drawback. First recipe has lower Id^ and lower St while second recipe has higher IDsat and higher St Higher W means the device can perform at taster speed while lower St. shows the device has good turn-off characteristics. Overall, the electrical parameters obtained are agreeable with ITRS requirement and other reported works except for the result ofW This could be due to the direct scaling. Other parameters such as St could not be compared as itis confidential to the public

Low-Frequency Noise Phenomena in Switched MOSFETs

In small-area MOSFETs widely used in analog and RF circuit design, low-frequency (LF) noise behavior is increasingly dominated by single-electron effects. In this paper, the authors review the limitations of current compact noise models which do not model such single-electron effects. The authors present measurement results that illustrate typical LF noise behavior in small-area MOSFETs, and a model based on Shockley-Read-Hall statistics to explain the behavior. Finally, the authors treat practical examples that illustrate the relevance of these effects to analog circuit design. To the analog circuit designer, awareness of these single-electron noise phenomena is crucial if optimal circuits are to be designed, especially since the effects can aid in low-noise circuit design if used properly, while they may be detrimental to performance if inadvertently applie

Room-Temperature Terahertz Detection and Imaging by Using Strained-Silicon MODFETs

This chapter reports on an experimental and theoretical study of Schottky-gated strained-Si modulation-doped field-effect transistors (MODFETs) with different sub-micron gate lengths (100, 250, and 500 nm). Room-temperature detection of terahertz (THz) radiation by the strained-Si MODFETs was performed at two frequencies (0.15 and 0.3 THz). A technology computer-aided design (TCAD) analysis based on a two-dimensional hydrodynamic model (HDM) was used to investigate the transistor response to THz radiation excitation. TCAD simulation was validated through comparison with DC and low-frequency AC measurements. It was found that the photoresponse of the transistors can be improved by applying a constant drain-to-source bias. This enhancement was observed both theoretically and experimentally. The HDM model satisfactorily describes the experimental dependence of the photoresponse on the excitation frequency, the gate bias, and the drain-to-source current bias. The coupling of the incoming THz radiation to the MODFETs was studied at 0.15 and 0.3 THz. Finally, to demonstrate the suitability of strained-Si MODFET for terahertz applications, an image sensor within a pixel-by-pixel terahertz imaging system for the inspection of hidden objects was used

Self-aligned silicidation of surround gate vertical MOSFETs for low cost RF applications

We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-?m lithography are compared with nonsilicided devices. A source–drain (S/D) activation anneal of 30 s at 1100 ?C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-?m lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar

Unified electrical model for the contact regions of staggered Thin Film Transistors

In this work, we propose an unified compact model, which includes the effects of both source and drain contact regions, to describe the electrical characteristics of staggered thin film transistors (TFTs). The model is based on a generic drift analytical expression that describes the intrinsic channel of the transistor. Despite the distributed two-dimensional nature of the contacts in staggered configurations, two-terminal components are usually preferred to model the source and drain contact regions. In this regard, a model based on versatile simple expressions that describe the current-voltage relations of both contact regions are proposed in this work. These expressions are based on the physics underlying a metal-organic-metal structure. They can be adapted to different transport conditions, such as ohmic, space-charge-limited transport or Schottky-like contacts. This adaptation is controlled with the value of a single parameter that modifies the concavity or convexity of these expressions. The model works together with an evolutionary parameter extraction procedure, presented in a previous work for TFTs with negligible drain contact effects, and adapted here to this proposed model for staggered transistors. The results of the model and the evolutionary procedure have been validated with published experimental data of different TFTs, mostly organic thin film transistors (OTFTs). The model and evolutionary procedure agrees with other procedures tested successfully in the literature which were defined to cope with specific kinds of contacts in the TFTs. In this regard, our model and evolutionary parameter extraction procedure unify these previous procedures.Departamento de Electrónica y Tecnología de Computadore

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT