Efficient Rewirings for Enhancing Synchronizability of Dynamical Networks

In this paper, we present an algorithm for optimizing synchronizability of complex dynamical networks. Based on some network properties, rewirings, i.e. eliminating an edge and creating a new edge elsewhere, are performed iteratively avoiding always self-loops and multiple edges between the same nodes. We show that the method is able to enhance the synchronizability of networks of any size and topological properties in a small number of steps that scales with the network size.Although we take the eigenratio of the Laplacian as the target function for optimization, we will show that it is also possible to choose other appropriate target functions exhibiting almost the same performance. The optimized networks are Ramanujan graphs, and thus, this rewiring algorithm could be used to produce Ramanujan graphs of any size and average degree

Architecture of a network-in-the-Loop environment for characterizing AC power system behavior

This paper describes the method by which a large hardware-in-the-loop environment has been realized for three-phase ac power systems. The environment allows an entire laboratory power-network topology (generators, loads, controls, protection devices, and switches) to be placed in the loop of a large power-network simulation. The system is realized by using a realtime power-network simulator, which interacts with the hardware via the indirect control of a large synchronous generator and by measuring currents flowing from its terminals. These measured currents are injected into the simulation via current sources to close the loop. This paper describes the system architecture and, most importantly, the calibration methodologies which have been developed to overcome measurement and loop latencies. In particular, a new "phase advance" calibration removes the requirement to add unwanted components into the simulated network to compensate for loop delay. The results of early commissioning experiments are demonstrated. The present system performance limits under transient conditions (approximately 0.25 Hz/s and 30 V/s to contain peak phase-and voltage-tracking errors within 5. and 1%) are defined mainly by the controllability of the synchronous generator

The Brain on Low Power Architectures - Efficient Simulation of Cortical Slow Waves and Asynchronous States

Efficient brain simulation is a scientific grand challenge, a parallel/distributed coding challenge and a source of requirements and suggestions for future computing architectures. Indeed, the human brain includes about 10^15 synapses and 10^11 neurons activated at a mean rate of several Hz. Full brain simulation poses Exascale challenges even if simulated at the highest abstraction level. The WaveScalES experiment in the Human Brain Project (HBP) has the goal of matching experimental measures and simulations of slow waves during deep-sleep and anesthesia and the transition to other brain states. The focus is the development of dedicated large-scale parallel/distributed simulation technologies. The ExaNeSt project designs an ARM-based, low-power HPC architecture scalable to million of cores, developing a dedicated scalable interconnect system, and SWA/AW simulations are included among the driving benchmarks. At the joint between both projects is the INFN proprietary Distributed and Plastic Spiking Neural Networks (DPSNN) simulation engine. DPSNN can be configured to stress either the networking or the computation features available on the execution platforms. The simulation stresses the networking component when the neural net - composed by a relatively low number of neurons, each one projecting thousands of synapses - is distributed over a large number of hardware cores. When growing the number of neurons per core, the computation starts to be the dominating component for short range connections. This paper reports about preliminary performance results obtained on an ARM-based HPC prototype developed in the framework of the ExaNeSt project. Furthermore, a comparison is given of instantaneous power, total energy consumption, execution time and energetic cost per synaptic event of SWA/AW DPSNN simulations when executed on either ARM- or Intel-based server platforms

Performance evaluation of wireless sensor networks for mobile event and mobile sink

Extending lifetime and energy efficiency are important objectives and challenges in-Wireless Sensor Networks (WSNs). In large scale WSNs, when the nodes are near to the sink they consume much more energy than the nodes far from the sink. In our previous work, we considered that the sink node was stationary and only event node was moving in the observation field. In this work, we consider both cases when the sink node and event node are moving. For the simulations, we use TwoRayGround and Shadowing radio models, lattice topology and AODV protocol. We compare the simulation results for the cases when the sink node and event node are mobile and stationary. The simulation results have shown that the goodput of TwoRayGround is better than Shadowing in case of mobile event, but the depletion of Shadowing is better than TwoRayGround in case of mobile event. The goodput in case of mobile sink is better than stationary sink when the transmission rate is lower than 10pps. For TwoRayGround radio model, the depletion in case of mobile sink is better than stationary sink when the number of nodes is increasedPeer ReviewedPostprint (published version

Design of Easily Synchronizable Oscillator Networks Using the Monte Carlo Optimization Method

Starting with an initial random network of oscillators with a heterogeneous frequency distribution, its autonomous synchronization ability can be largely improved by appropriately rewiring the links between the elements. Ensembles of synchronization-optimized networks with different connectivities are generated and their statistical properties are studied