Flexible scheduling of turbo decoding on a multiprocessor platform

Basic concepts and literature review -- Universal mobile telecommunication system (UMTS) -- The vocallo architecture -- Performance modeling -- Mapping the system level models into MPSoC platforms -- Multiprocessor scheduling and synchronization -- Worst case execution time (WCET) based design -- Scheduling flexible applications -- Mapping and scheduling of turbo decoding in MPSoC platforms -- Performance modeling -- Steps to create a performance model -- Detailed description of the performance model -- One performance model example -- Scheduling of turbo decoding -- Mapping the uplink WCDMA processing on an MPSoC platform -- Processing variability of the studied turbo decoder -- BER performance of the studied turbo decoder -- Proposed methods for scheduling the turbo decoding -- Simulation results -- Validating investigation -- Elapsed simulation time

Soft-demodulation of QPSK and 16-QAM for turbo coded WCDMA mobile communication systems

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Modified VLSI designs for error correction codes

Nowadays, error correction codes have become an integral part in almost all the modern digital communication and storage systems. With the continuously increasing demands for higher speed and lower power communication systems, efficient VLSI implementations of those error correction codes have great importance for practical applications. In this thesis, several VLSI design issues for Viterbi decoder and Low-Density Parity-Check (LDPC) codes decoder will be discussed. We propose a low-power memory-efficient Viterbi decoder to reduce the memory read operations in the survivor memory unit (SMU) and the memory size of SMU. We develop a parallel Viterbi decoder for high throughput applications. We also propose an efficient early stopping scheme to reduce the number of decoding iterations for LDPC codes decoding

Coded Parity Packet Transmission Method for Two Group Resource Allocation

Gap value control is investigated when the number of source and parity packets is adjusted in a concatenated coding scheme whilst keeping the overall coding rate fixed. Packet-based outer codes which are generated from bit-wise XOR combinations of the source packets are used to adjust the number of both source packets. Having the source packets, the number of parity packets, which are the bit-wise XOR combinations of the source packets can be adjusted such that the gap value, which measures the gap between the theoretical and the required signal-to-noise ratio (SNR), is controlled without changing the actual coding rate. Consequently, the required SNR reduces, yielding a lower required energy to realize the transmission data rate. Integrating this coding technique with a two-group resource allocation scheme renders efficient utilization of the total energy to further improve the data rates. With a relatively small-sized set of discrete data rates, the system throughput achieved by the proposed two-group loading scheme is observed to be approximately equal to that of the existing loading scheme, which is operated with a much larger set of discrete data rates. The gain obtained by the proposed scheme over the existing equal rate and equal energy loading scheme is approximately 5 dB. Furthermore, a successive interference cancellation scheme is also integrated with this coding technique, which can be used to decode and provide consecutive symbols for inter-symbol interference (ISI) and multiple access interference (MAI) mitigation. With this integrated scheme, the computational complexity is signi cantly reduced by eliminating matrix inversions. In the same manner, the proposed coding scheme is also incorporated into a novel fixed energy loading, which distributes packets over parallel channels, to control the gap value of the data rates although the SNR of each code channel varies from each other