Survey of switching techniques in high-speed networks and their performance

One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (Asynchronous Transfer Mode). ATM can be characterized by very high speed transmission links and simple, hard wired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks.A number of designs has been proposed for implementing ATM switches. While many differences exist among the proposals, the vast majority of them is based on self-routing multi-stage interconnection networks. This is because of the desirable features of multi-stage interconnection networks such as self-routing capability and suitability for VLSI implementation.Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more than one cell contends for the same internal link, and non-blocking switches, where no internal blocking occurs. A large number of techniques has also been proposed to improve the performance of blocking and nonblocking switches. In this paper, we present an extensive survey of the existing proposals for ATM switch architectures, focusing on their performance issues

Multicast cross-path ATM switches: principles, designs and performance evaluations.

by Lin Hon Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 59-[63]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Organization of Thesis --- p.3Chapter 2 --- Principles of Multicast Cross-Path Switches --- p.4Chapter 2.1 --- Introduction --- p.4Chapter 2.2 --- Unicast Cross-Path switch --- p.5Chapter 2.2.1 --- Routing properties in Clos networks --- p.5Chapter 2.2.2 --- Quasi-static routing procedures --- p.5Chapter 2.2.3 --- Capacity and Route Assignment --- p.7Chapter 2.3 --- Multicast Cross-Path Switch --- p.8Chapter 2.3.1 --- Scheme 1 - Cell replication performed at both input and output stages --- p.10Chapter 2.3.2 --- Scheme 2 - Cell replication performed only at the input stage --- p.10Chapter 3 --- Architectures --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Input Module Design (Scheme 1) --- p.16Chapter 3.2.1 --- Input Header Translator --- p.16Chapter 3.2.2 --- Input Module Controller --- p.17Chapter 3.2.3 --- Input Replication Network (Scheme 1) --- p.19Chapter 3.2.4 --- Routing Network --- p.23Chapter 3.3 --- Central Modules --- p.24Chapter 3.4 --- Output Module Design (Scheme 1) --- p.24Chapter 3.5 --- Input Module Design (Scheme 2) --- p.25Chapter 3.5.1 --- Input Header Translator (Scheme 2) --- p.26Chapter 3.5.2 --- Input Module Controller (Scheme 2) --- p.27Chapter 3.5.3 --- Input Replication Network (Scheme 2) --- p.28Chapter 3.6 --- Output Module Design (Scheme 2) --- p.29Chapter 4 --- Performance Evaluations --- p.31Chapter 4.1 --- Introduction --- p.31Chapter 4.2 --- Traffic characteristics --- p.31Chapter 4.2.1 --- Fanout distribution --- p.31Chapter 4.2.2 --- Middle stage traffic load and its calculation --- p.32Chapter 4.3 --- Throughput Performance --- p.34Chapter 4.4 --- Delay Performance --- p.37Chapter 4.4.1 --- Input Stage Delay --- p.38Chapter 4.4.2 --- Output Stage Delay --- p.39Chapter 4.5 --- Cell Loss Performance --- p.43Chapter 4.5.1 --- Cell Loss due to Buffer Overflow --- p.44Chapter 4.5.2 --- Cell Loss Due to Output Contention --- p.45Chapter 4.6 --- Complexities --- p.50Chapter 5 --- Conclusions --- p.57Bibliography --- p.5

A formalism for describing and simulating systems with interacting components.

This thesis addresses the problem of descriptive complexity presented by systems involving a high number of interacting components. It investigates the evaluation measure of performability and its application to such systems. A new description and simulation language, ICE and it's application to performability modelling is presented. ICE (Interacting ComponEnts) is based upon an earlier description language which was first proposed for defining reliability problems. ICE is declarative in style and has a limited number of keywords. The ethos in the development of the language has been to provide an intuitive formalism with a powerful descriptive space. The full syntax of the language is presented with discussion as to its philosophy. The implementation of a discrete event simulator using an ICE interface is described, with use being made of examples to illustrate the functionality of the code and the semantics of the language. Random numbers are used to provide the required stochastic behaviour within the simulator. The behaviour of an industry standard generator within the simulator and different methods of number allocation are shown. A new generator is proposed that is a development of a fast hardware shift register generator and is demonstrated to possess good statistical properties and operational speed. For the purpose of providing a rigorous description of the language and clarification of its semantics, a computational model is developed using the formalism of extended coloured Petri nets. This model also gives an indication of the language's descriptive power relative to that of a recognised and well developed technique. Some recognised temporal and structural problems of system event modelling are identified. and ICE solutions given. The growing research area of ATM communication networks is introduced and a sophisticated top down model of an ATM switch presented. This model is simulated and interesting results are given. A generic ICE framework for performability modelling is developed and demonstrated. This is considered as a positive contribution to the general field of performability research

A Performance evaluation of several ATM switching architectures

The goal of this thesis is to evaluate the performance of three Asynchronous Transfer Mode switching architectures. After examining many different ATM switching architectures in literature, the three architectures chosen for study were the Knockout switch, the Sunshine switch, and the Helical switch. A discrete-time, event driven system simulator, named ProModel, was used to model the switching behavior of these architectures. Each switching architecture was modeled and studied under at least two design configurations. The performance of the three architectures was then investigated under three different traffic types representative of traffic found in B-ISDN: random, constant bit rate, and bursty. Several key performance parameters were measured and compared between the architectures. This thesis also explored the implementation complexities and fault tolerance of the three selected architectures

Analysis of power consumption on switch fabrics in network routers

In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, internal buffers and interconnect wires inside switch fabric architectures. A simulation platform is also implemented to trace the dynamic power consumption with bit-level accuracy. Using this framework, four switch fabric architectures are analyzed under different traffic throughput and different numbers of ingress/egress ports. This framework and analysis can be applied to the architectural exploration for low power high performance network router designs

The AURORA Gigabit Testbed

AURORA is one of five U.S. networking testbeds charged with exploring applications of, and technologies necessary for, networks operating at gigabit per second or higher bandwidths. The emphasis of the AURORA testbed, distinct from the other four testbeds, BLANCA, CASA, NECTAR, and VISTANET, is research into the supporting technologies for gigabit networking. Like the other testbeds, AURORA itself is an experiment in collaboration, where government initiative (in the form of the Corporation for National Research Initiatives, which is funded by DARPA and the National Science Foundation) has spurred interaction among pre-existing centers of excellence in industry, academia, and government. AURORA has been charged with research into networking technologies that will underpin future high-speed networks. This paper provides an overview of the goals and methodologies employed in AURORA, and points to some preliminary results from our first year of research, ranging from analytic results to experimental prototype hardware. This paper enunciates our targets, which include new software architectures, network abstractions, and hardware technologies, as well as applications for our work

Analyzing Traffic and Multicast Switch Issues in an ATM Network.

This dissertation attempts to solve two problems related to an ATM network. First, we consider packetized voice and video sources as the incoming traffic to an ATM multiplexer and propose modeling methods for both individual and aggregated traffic sources. These methods are, then, used to analyze performance parameters such as buffer occupancy, cell loss probability, and cell delay. Results, thus obtained, for different buffer sizes and number of voice and video sources are analyzed and compared with those generated from existing techniques. Second, we study the priority handling feature for time critical services in an ATM multicast switch. For this, we propose a non-blocking copy network and priority handling algorithms. We, then, analyze the copy network using an analytical method and simulation. The analysis utilizes both priority and non-priority cells for two different output reservation schemes. The performance parameters, based on cell delay, delay jitter, and cell loss probability, are studied for different buffer sizes and fan-outs under various input traffic loads. Our results show that the proposed copy network provides a better performance for the priority cells while the performance for the non-priority cells is slightly inferior in comparison with the scenario when the network does not consider priority handling. We also study the fault-tolerant behavior of the copy network, specially for the broadcast banyan network subsection, and present a routing scheme considering the non-blocking property under a specific pattern of connection assignments. A fault tolerant characteristic can be quantified using the full access probability. The computation of the full access probability for a general network is known to be NP-hard. We, therefore, provide a new bounding technique utilizing the concept of minimal cuts to compute full access probability of the copy network. Our study for the fault-tolerant multi-stage interconnection network having either an extra stage or chaining shows that the proposed technique provides tighter bounds as compared to those given by existing approaches. We also apply our bounding method to compute full access probability of the fault-tolerant copy network

Design and analysis of a scalable terabit multicast packet switch : architecture and scheduling algorithms

Internet growth and success not only open a primary route of information exchange for millions of people around the world, but also create unprecedented demand for core network capacity. Existing switches/routers, due to the bottleneck from either switch architecture or arbitration complexity, can reach a capacity on the order of gigabits per second, but few of them are scalable to large capacity of terabits per second. In this dissertation, we propose three novel switch architectures with cooperated scheduling algorithms to design a terabit backbone switch/router which is able to deliver large capacity, multicasting, and high performance along with Quality of Service (QoS). Our switch designs benefit from unique features of modular switch architecture and distributed resource allocation scheme. Switch I is a unique and modular design characterized by input and output link sharing. Link sharing resolves output contention and eliminates speedup requirement for central switch fabric. Hence, the switch architecture is scalable to any large size. We propose a distributed round robin (RR) scheduling algorithm which provides fairness and has very low arbitration complexity. Switch I can achieve good performance under uniform traffic. However, Switch I does not perform well for non-uniform traffic. Switch II, as a modified switch design, employs link sharing as well as a token ring to pursue a solution to overcome the drawback of Switch 1. We propose a round robin prioritized link reservation (RR+POLR) algorithm which results in an improved performance especially under non-uniform traffic. However, RR+POLR algorithm is not flexible enough to adapt to the input traffic. In Switch II, the link reservation rate has a great impact on switch performance. Finally, Switch III is proposed as an enhanced switch design using link sharing and dual round robin rings. Packet forwarding is based on link reservation. We propose a queue occupancy based dynamic link reservation (QOBDLR) algorithm which can adapt to the input traffic to provide a fast and fair link resource allocation. QOBDLR algorithm is a distributed resource allocation scheme in the sense that dynamic link reservation is carried out according to local available information. Arbitration complexity is very low. Compared to the output queued (OQ) switch which is known to offer the best performance under any traffic pattern, Switch III not only achieves performance as good as the OQ switch, but also overcomes speedup problem which seriously limits the OQ switch to be a scalable switch design. Hence, Switch III would be a good choice for high performance, scalable, large-capacity core switches

Distributed call set-up algorithms in BISDN environment.

by Shum Kam Hong.Thesis (M.Phil.)--Chinese University of Hong Kong, 1992.Includes bibliographical references (leaves 125-131).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Outline of the thesis --- p.6Chapter 1.3 --- Current Art in Packet Switching --- p.9Chapter 2 --- Management of Control Information --- p.17Chapter 2.1 --- Inter-node Exchange of Link Congestion Status --- p.21Chapter 2.2 --- Consistency of Control Information --- p.24Chapter 2.3 --- Alternate Format of Control Information --- p.26Chapter 3 --- Traffic Flow Control --- p.29Chapter 3.1 --- Control of Traffic Influx into the Network --- p.29Chapter 3.2 --- Control of Traffic Loading from the Node --- p.30Chapter 3.3 --- Flow Control for Connection Oriented Traffic --- p.32Chapter 3.4 --- Judgement of Link Status --- p.38Chapter 3.5 --- Starvation-free and Deadlock-free --- p.42Chapter 4 --- Call Set-up Algorithm Traffic Modelling --- p.47Chapter 4.1 --- Basic Algorithm --- p.47Chapter 4.2 --- Minimization of Bandwidth Overhead --- p.48Chapter 4.3 --- Two-way Transmission --- p.51Chapter 4.4 --- Traffic Modelling --- p.52Chapter 4.4.1 --- Aggregate Traffic Models --- p.53Chapter 4.4.2 --- Traffic Burstiness --- p.57Chapter 5 --- Parameters Tuning and Analysis --- p.76Chapter 5.1 --- Scheme I : Scout Pumping --- p.76Chapter 5.2 --- Scheme II : Speed-up Scout Pumping --- p.85Chapter 5.3 --- Blocking Probability --- p.90Chapter 5.4 --- Scout Stream Collision --- p.92Chapter 6 --- Simulation Modelling & Performance Evaluation --- p.96Chapter 6.1 --- The Network Simulator --- p.96Chapter 6.1.1 --- Simulation Event Scheduling --- p.97Chapter 6.1.2 --- Input Traffic Regulation --- p.100Chapter 6.1.3 --- Actual Offered Load --- p.101Chapter 6.1.4 --- Static and Dynamic Parameters --- p.103Chapter 6.2 --- Simulation Results --- p.107Chapter 7 --- Conclusions --- p.123Chapter A --- List of Symbols --- p.13

Novel techniques in large scaleable ATM switches

Bibliography: p. 172-178.This dissertation explores the research area of large scale ATM switches. The requirements for an ATM switch are determined by overviewing the ATM network architecture. These requirements lead to the discussion of an abstract ATM switch which illustrates the components of an ATM switch that automatically scale with increasing switch size (the Input Modules and Output Modules) and those that do not (the Connection Admission Control and Switch Management systems as well as the Cell Switch Fabric). An architecture is suggested which may result in a scalable Switch Management and Connection Admission Control function. However, the main thrust of the dissertation is confined to the cell switch fabric. The fundamental mathematical limits of ATM switches and buffer placement is presented next emphasising the desirability of output buffering. This is followed by an overview of the possible routing strategies in a multi-stage interconnection network. A variety of space division switches are then considered which leads to a discussion of the hypercube fabric, (a novel switching technique). The hypercube fabric achieves good performance with an O(N.log₂N)²) scaling. The output module, resequencing, cell scheduling and output buffering technique is presented leading to a complete description of the proposed ATM switch. Various traffic models are used to quantify the switch's performance. These include a simple exponential inter-arrival time model, a locality of reference model and a self-similar, bursty, multiplexed Variable Bit Rate (VBR) model. FIFO queueing is simple to implement in an ATNI switch, however, more responsive queueing strategies can result in an improved performance. An associative memory is presented which allows the separate queues in the ATM switch to be effectively logically combined into a single FIFO queue. The associative memory is described in detail and its feasibility is shown by laying out the Integrated Circuit masks and performing an analogue simulation of the IC's performance is SPICE3. Although optimisations were required to the original design, the feasibility of the approach is shown with a 15Ƞs write time and a 160Ƞs read time for a 32 row, 8 priority bit, 10 routing bit version of the memory. This is achieved with 2µm technology, more advanced technologies may result in even better performance. The various traffic models and switch models are simulated in a number of runs. This shows the performance of the hypercube which outperforms a Clos network of equivalent technology and approaches the performance of an ideal reference fabric. The associative memory leverages a significant performance advantage in the hypercube network and a modest advantage in the Clos network. The performance of the switches is shown to degrade with increasing traffic density, increasing locality of reference, increasing variance in the cell rate and increasing burst length. Interestingly, the fabrics show no real degradation in response to increasing self similarity in the fabric. Lastly, the appendices present suggestions on how redundancy, reliability and multicasting can be achieved in the hypercube fabric. An overview of integrated circuits is provided. A brief description of commercial ATM switching products is given. Lastly, a road map to the simulation code is provided in the form of descriptions of the functionality found in all of the files within the source tree. This is intended to provide the starting ground for anyone wishing to modify or extend the simulation system developed for this thesis