A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

π-Clamp-mediated cysteine conjugation

Site-selective functionalization of complex molecules is one of the most significant challenges in chemistry. Typically, protecting groups or catalysts must be used to enable the selective modification of one site among many that are similarly reactive, and general strategies that selectively tune the local chemical environment around a target site are rare. Here, we show a four-amino-acid sequence (Phe-Cys-Pro-Phe), which we call the ‘π-clamp’, that tunes the reactivity of its cysteine thiol for site-selective conjugation with perfluoroaromatic reagents. We use the π-clamp to selectively modify one cysteine site in proteins containing multiple endogenous cysteine residues. These examples include antibodies and cysteine-based enzymes that would be difficult to modify selectively using standard cysteine-based methods. Antibodies modified using the π-clamp retained binding affinity to their targets, enabling the synthesis of site-specific antibody–drug conjugates for selective killing of HER2-positive breast cancer cells. The π-clamp is an unexpected approach to mediate site-selective chemistry and provides new avenues to modify biomolecules for research and therapeutics.Massachusetts Institute of Technology (Start-up Funds)National Institutes of Health (U.S.) (NIH R01GM110535)Sontag Foundation (Distinguished Scientist Award)Massachusetts Institute of Technology. Department of Chemistry (George Buchi Research Fellowship)David H. Koch Institute for Integrative Cancer Research at MIT (Graduate Fellowship)Bristol-Myers Squibb Company (Graduate Fellowship in Synthetic Organic Chemistry)National Science Foundation (U.S.) (Graduate Research Fellow

Physical properties of eclipsing white dwarf binaries

Close binaries containing compact objects come in many different forms, but have one thing in common: their evolution involves at least one common envelope phase and angular momentum losses. However, many aspects of these two fundamental processes are still poorly understood. Ample observational input holds the key to improving our understanding, as only then can theoretical models be properly calibrated and tested. Close binaries containing a white dwarf are perhaps the best-suited class of objects to provide such input, due to their ubiquity. White dwarf binaries that additionally display eclipses are of added interest, as accurate and model-independent determinations of fundamental stellar parameters, such as the masses and radii of the binary components, can only be obtained in such systems. In this thesis, I present a study of eclipsing white dwarf binaries. I identify SDSSJ 0110+1326, SDSSJ 0303+0054, SDSSJ 1210+3347, SDSSJ 1435+3733 and SDSSJ 1548+4057 as new eclipsing, detached, post-common-envelope, white dwarf +M-dwarf binaries. I use follow-up photometric and spectroscopic observations, as well as a light curve fitting technique to measure their orbital periods, and derive the masses, radii and radial velocities of the binary components. These five systems have been identified as part of the first dedicated search for eclipsing post-common-envelope binaries and almost double the existing population. The measurements of the stellar parameters, and others obtained from similar systems, are of great value both for the calibration of the common envelope equations and for testing the mass-radius relations of white dwarfs and low-mass main sequence stars. I also identify HS 2325+8205 as a new eclipsing and very frequently outbursting dwarf nova. Combined constraints from photometric and spectroscopic observations are used to infer the binary and stellar parameters. The combination of eclipses, frequent outbursts, brightness range and high declination make HS 2325+8205 an ideal laboratory for detailed studies of accretion discs and accretion processes in close binaries. Finally I study the cataclysmic variable V455And, in an attempt to verify the presence of non-radial pulsations in the white dwarf primary. This is achieved by analysing ten-years worth of photometric observations using time-series analysis techniques and Fourier transforms. The results are indeed consistent with white dwarf pulsations, although a very complex behaviour of the power spectra is revealed, most likely a result of the rapid rotation of the accreting white dwarf primary