TOWARDS A NOVEL RESILIENT ROBOTIC SYSTEM

Resilient robotic systems are a kind of robotic system that is able to recover their original function after partial damage of the system. This is achieved by making changes on the partially damaged robot. In this dissertation study, a general robot, which makes sense by including active joints, passive joints, passive links, and passive adjustable links, was proposed in order to explore its resilience. Note that such a robot is also called an under-actuated robot. This dissertation presents the following studies. First, a novel architecture of robots was proposed, which is characterized as under-actuated robot. The architecture enables three types of recovery strategy, namely (1) change of the robot behavior, (2) change of the robot state, and (3) change of the robot configuration. Second, a novel docking system was developed, which allows for the realization of real-time assembly and disassembly and passive joint and adjustable passive link, and this thus enables the realization of the proposed architecture. Third, an example prototype system was built to experiment the effectiveness of the proposed architecture and to demonstrate the resilient behavior of the robot. Fourth, a novel method for robot configuration synthesis was developed, which is based on the genetic algorithm (GA), to determine the goal configuration of a partially damaged robot, at which the robot can still perform its original function. The novelty of the method lies in the integration of both discrete variables such as the number of modules, type of modules, and assembly patterns between modules and the continuous variables such as the length of modules and initial location of the robot. Fifth, a GA-based method for robot reconfiguration planning and scheduling was developed to actually change the robot from its initial configuration to the goal configuration with a minimum effort (time and energy). Two conclusions can be drawn from the above studies. First, the under-actuated robotic architecture can build a cost effective robot that can achieve the highest degree of resilience. Second, the design of the under-actuated resilient robot with the proposed docking system not only reduces the cost but also overcomes the two common actuator failures: (i) an active joint is unlocked (thus becoming a passive joint) and (ii) an active joint is locked (thus becoming an adjustable link). There are several contributions made by this dissertation to the field of robotics. The first is the finding that an under-actuated robot can be made more resilient. In the field of robotics, the concept of the under-actuated robot is available, but it has not been considered for reconfiguration (in literature, the reconfiguration is mostly about fully actuated robots). The second is the elaboration on the concept of reconfiguration planning, scheduling, and manipulation/control. In the literature of robotics, only the concept of reconfiguration planning is precisely given but not for reconfiguration scheduling. The third is the development of the model along with its algorithm for synthesis of the goal reconfiguration, reconfiguration planning, and scheduling. The application of the proposed under-actuated resilient robot lies in the operations in unknown or dangerous environments, for example, in rescue missions and space explorations. In these applications, replacement or repair of a damaged robot is impossible or cost-prohibited

Autonomous Recovery Of Reconfigurable Logic Devices Using Priority Escalation Of Slack

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria

Tool-Based Design and Evaluation of Resilient Flight Control Systems

Communications engineering / telecommunication

Chapter Tool-Based Design and Evaluation of Resilient Flight Control Systems

Communications engineering / telecommunication

Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures

The impact of SRAM-based FPGAs is constantly growing in aerospace industry despite the fact that their volatile configuration memory is highly susceptible to radiation effects. Therefore, strong fault-handling mechanisms have to be developed in order to protect the design and make it capable of fighting against both soft and permanent errors. In this paper, a fully reconfigurable medium-grained triple modular redundancy (TMR) architecture which forms part of a runtime adaptive on-board processor (OBP) is presented. Fault mitigation is extended to the voting mechanism by applying our reconfiguration methodology not only to domain replicas but also to the voter itself. The proposed approach takes advantage of adaptive configuration placement and modular property of the OBP, thus allowing on-line creation of different medium-grained TMRs and selection of their granularity level. Consequently, we are able to narrow down the fault-affected area thus making the error recovery process faster and less power consuming. The conventional hardware based voting is supported by the ICAP-based one in order to additionally strengthen the reconfigurable intermediate voting. In addition, the implementation methodology ensures using only one memory footprint for all voters and their voting adaptations thus saving storing resources in expensive rad-hard memories

Dynamic Partial Reconfiguration for Dependable Systems

Moore’s law has served as goal and motivation for consumer electronics manufacturers in the last decades. The results in terms of processing power increase in the consumer electronics devices have been mainly achieved due to cost reduction and technology shrinking. However, reducing physical geometries mainly affects the electronic devices’ dependability, making them more sensitive to soft-errors like Single Event Transient (SET) of Single Event Upset (SEU) and hard (permanent) faults, e.g. due to aging effects. Accordingly, safety critical systems often rely on the adoption of old technology nodes, even if they introduce longer design time w.r.t. consumer electronics. In fact, functional safety requirements are increasingly pushing industry in developing innovative methodologies to design high-dependable systems with the required diagnostic coverage. On the other hand commercial off-the-shelf (COTS) devices adoption began to be considered for safety-related systems due to real-time requirements, the need for the implementation of computationally hungry algorithms and lower design costs. In this field FPGA market share is constantly increased, thanks to their flexibility and low non-recurrent engineering costs, making them suitable for a set of safety critical applications with low production volumes. The works presented in this thesis tries to face new dependability issues in modern reconfigurable systems, exploiting their special features to take proper counteractions with low impacton performances, namely Dynamic Partial Reconfiguration

Restructurable Controls

Restructurable control system theory, robust reconfiguration for high reliability and survivability for advanced aircraft, restructurable controls problem definition and research, experimentation, system identification methods applied to aircraft, a self-repairing digital flight control system, and state-of-the-art theory application are addressed

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs

SRAM-based FPGAs are sensitive to radiation effects. Soft errors can appear and accumulate, potentially defeating mitigation strategies deployed at the Application Layer. Therefore, Configuration Memory scrubbing is required to improve radiation tolerance of such FPGAs in space applications. Virtex FPGAs allow runtime scrubbing by means of dynamic partial reconfiguration. Even with scrubbing, intra-FPGA TMR systems are subjected to common-mode errors affecting more than one design domain. This is solved in inter-FPGA TMR systems at the expense of a higher cost, power and mass. In this context, a self-reference scrubber for device-level TMR system based on Xilinx Virtex FPGAs is presented. This scrubber allows for a fast SEU/MBU detection and correction by peer frame comparison without needing to access a golden configuration memor