On the aeroacoustic and flow structures developed on a flat plate with a serrated sawtooth trailing edge

Open Access funded by Engineering and Physical Sciences Research Council.Results of an experimental study on turbulent flow over a flat plate with a serrated sawtooth trailing edge are presented in this paper. After tripping the boundary layer to become turbulent, the broadband noise sources at the sawtooth serrated trailing edge is studied by several experimental techniques. Broadband noise reduction by the serrated sawtooth trailing edge can be realistically achieved in the flat plate configuration. The variations of wall pressure power spectral density and the spanwise coherence (which relates to the spanwise correlation length) in a sawtooth trailing edge play a minor role in the mechanisms underpinning the reduction of self noise radiation. Conditional-averaging technique was applied in the boundary layer data where a pair of pressure-driven oblique vortical structures near the sawtooth side edges is identified. In the current flat plate configuration, the interaction between the vortical structures and the local turbulent boundary layer results in a redistribution of the momentum transport and turbulent shear stress near the sawtooth side edges as well as the sawtooth tip, thus affecting the efficiency of self noise radiation.The authors are grateful for the support from the EPSRC Doctoral Training Grants in the United Kingdom

Bond Breaking Kinetics in Mechanically Controlled Break Junction Experiments: A Bayesian Approach

Breakjunction experiments allow investigating electronic and spintronic properties at the atomic and molecular scale. These experiments generate by their very nature broad and asymmetric distributions of the observables of interest, and thus a full statistical interpretation is warranted. We show here that understanding the complete distribution is essential for obtaining reliable estimates. We demonstrate this for Au atomic point contacts, where by adopting Bayesian reasoning we can reliably estimate the distance to the transition state, $x{\ddag}$, the associated free energy barrier, ${\Delta}G{\ddag}$, and the curvature $\nu$ of the free energy surface. Obtaining robust estimates requires less experimental effort than with previous methods, fewer assumptions, and thus leads to a significant reassessment of the kinetic parameters in this paradigmatic atomic-scale structure. Our proposed Bayesian reasoning offers a powerful and general approach when interpreting inherently stochastic data that yield broad, asymmetric distributions for which analytical models of the distribution may be developed

Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

Circuit design and analysis for on-FPGA communication systems

On-chip communication system has emerged as a prominently important subject in Very-Large- Scale-Integration (VLSI) design, as the trend of technology scaling favours logics more than interconnects. Interconnects often dictates the system performance, and, therefore, research for new methodologies and system architectures that deliver high-performance communication services across the chip is mandatory. The interconnect challenge is exacerbated in Field-Programmable Gate Array (FPGA), as a type of ASIC where the hardware can be programmed post-fabrication. Communication across an FPGA will be deteriorating as a result of interconnect scaling. The programmable fabrics, switches and the specific routing architecture also introduce additional latency and bandwidth degradation further hindering intra-chip communication performance. Past research efforts mainly focused on optimizing logic elements and functional units in FPGAs. Communication with programmable interconnect received little attention and is inadequately understood. This thesis is among the first to research on-chip communication systems that are built on top of programmable fabrics and proposes methodologies to maximize the interconnect throughput performance. There are three major contributions in this thesis: (i) an analysis of on-chip interconnect fringing, which degrades the bandwidth of communication channels due to routing congestions in reconfigurable architectures; (ii) a new analogue wave signalling scheme that significantly improves the interconnect throughput by exploiting the fundamental electrical characteristics of the reconfigurable interconnect structures. This new scheme can potentially mitigate the interconnect scaling challenges. (iii) a novel Dynamic Programming (DP)-network to provide adaptive routing in network-on-chip (NoC) systems. The DP-network architecture performs runtime optimization for route planning and dynamic routing which, effectively utilizes the in-silicon bandwidth. This thesis explores a new horizon in reconfigurable system design, in which new methodologies and concepts are proposed to enhance the on-FPGA communication throughput performance that is of vital importance in new technology processes

Skyrmion Hall Effect Revealed by Direct Time-Resolved X-Ray Microscopy

Magnetic skyrmions are highly promising candidates for future spintronic applications such as skyrmion racetrack memories and logic devices. They exhibit exotic and complex dynamics governed by topology and are less influenced by defects, such as edge roughness, than conventionally used domain walls. In particular, their finite topological charge leads to a predicted "skyrmion Hall effect", in which current-driven skyrmions acquire a transverse velocity component analogous to charged particles in the conventional Hall effect. Here, we present nanoscale pump-probe imaging that for the first time reveals the real-time dynamics of skyrmions driven by current-induced spin orbit torque (SOT). We find that skyrmions move at a well-defined angle {\Theta}_{SH} that can exceed 30{\deg} with respect to the current flow, but in contrast to theoretical expectations, {\Theta}_{SH} increases linearly with velocity up to at least 100 m/s. We explain our observation based on internal mode excitations in combination with a field-like SOT, showing that one must go beyond the usual rigid skyrmion description to unravel the dynamics.Comment: pdf document arxiv_v1.1. 24 pages (incl. 9 figures and supplementary information

Aeronautical engineering: A special bibliography with indexes, supplement 80

This bibliography lists 277 reports, articles, and other documents introduced into the NASA scientific and technical information system in January 1977

Machine Learning-Based Data and Model Driven Bayesian Uncertanity Quantification of Inverse Problems for Suspended Non-structural System

Inverse problems involve extracting the internal structure of a physical system from noisy measurement data. In many fields, the Bayesian inference is used to address the ill-conditioned nature of the inverse problem by incorporating prior information through an initial distribution. In the nonparametric Bayesian framework, surrogate models such as Gaussian Processes or Deep Neural Networks are used as flexible and effective probabilistic modeling tools to overcome the high-dimensional curse and reduce computational costs. In practical systems and computer models, uncertainties can be addressed through parameter calibration, sensitivity analysis, and uncertainty quantification, leading to improved reliability and robustness of decision and control strategies based on simulation or prediction results. However, in the surrogate model, preventing overfitting and incorporating reasonable prior knowledge of embedded physics and models is a challenge. Suspended Nonstructural Systems (SNS) pose a significant challenge in the inverse problem. Research on their seismic performance and mechanical models, particularly in the inverse problem and uncertainty quantification, is still lacking. To address this, the author conducts full-scale shaking table dynamic experiments and monotonic & cyclic tests, and simulations of different types of SNS to investigate mechanical behaviors. To quantify the uncertainty of the inverse problem, the author proposes a new framework that adopts machine learning-based data and model driven stochastic Gaussian process model calibration to quantify the uncertainty via a new black box variational inference that accounts for geometric complexity measure, Minimum Description length (MDL), through Bayesian inference. It is validated in the SNS and yields optimal generalizability and computational scalability