Switchable Genetic Oscillator Operating in Quasi-Stable Mode

Ring topologies of repressing genes have qualitatively different long-term dynamics if the number of genes is odd (they oscillate) or even (they exhibit bistability). However, these attractors may not fully explain the observed behavior in transient and stochastic environments such as the cell. We show here that even repressilators possess quasi-stable, travelling-wave periodic solutions that are reachable, long-lived and robust to parameter changes. These solutions underlie the sustained oscillations observed in even rings in the stochastic regime, even if these circuits are expected to behave as switches. The existence of such solutions can also be exploited for control purposes: operation of the system around the quasi-stable orbit allows us to turn on and off the oscillations reliably and on demand. We illustrate these ideas with a simple protocol based on optical interference that can induce oscillations robustly both in the stochastic and deterministic regimes.Comment: 24 pages, 5 main figure

Formal Verification of Probabilistic SystemC Models with Statistical Model Checking

Transaction-level modeling with SystemC has been very successful in describing the behavior of embedded systems by providing high-level executable models, in which many of them have inherent probabilistic behaviors, e.g., random data and unreliable components. It thus is crucial to have both quantitative and qualitative analysis of the probabilities of system properties. Such analysis can be conducted by constructing a formal model of the system under verification and using Probabilistic Model Checking (PMC). However, this method is infeasible for large systems, due to the state space explosion. In this article, we demonstrate the successful use of Statistical Model Checking (SMC) to carry out such analysis directly from large SystemC models and allow designers to express a wide range of useful properties. The first contribution of this work is a framework to verify properties expressed in Bounded Linear Temporal Logic (BLTL) for SystemC models with both timed and probabilistic characteristics. Second, the framework allows users to expose a rich set of user-code primitives as atomic propositions in BLTL. Moreover, users can define their own fine-grained time resolution rather than the boundary of clock cycles in the SystemC simulation. The third contribution is an implementation of a statistical model checker. It contains an automatic monitor generation for producing execution traces of the model-under-verification (MUV), the mechanism for automatically instrumenting the MUV, and the interaction with statistical model checking algorithms.Comment: Journal of Software: Evolution and Process. Wiley, 2017. arXiv admin note: substantial text overlap with arXiv:1507.0818

Timed event-graph and performance evaluation of systems

Bibliography: p. 16.Suppport provided by the Joint Director's Laboratories under contract no. N00014-85-K-0782 Support provided by the Office of Naval Research under contract no. N00014-84-K-0519by Herve P. Hillion, Alexander H. Levis

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Performance evaluation of decisionmaking organizations

Caption title.Bibliography: p. 7-8.Supported, in part, by a contract from the Office of Naval Research. N00014-85-K-0519 Supported, in part, by a contract from the Joint Directors of Laboraties through the Office of Naval Research. N00014-85-K-0782by Herve P. Hillion, Alexander H. Levis

Hybrid Petri net model of a traffic intersection in an urban network

Control in urban traffic networks constitutes an important and challenging research topic nowadays. In the literature, a lot of work can be found devoted to improving the performance of the traffic flow in such systems, by means of controlling the red-to-green switching times of traffic signals. Different techniques have been proposed and commercially implemented, ranging from heuristic methods to model-based optimization. However, given the complexity of the dynamics and the scale of urban traffic networks, there is still a lot of scope for improvement. In this work, a new hybrid model for the traffic behavior at an intersection is introduced. It captures important aspects of the flow dynamics in urban networks. It is shown how this model can be used in order to obtain control strategies that improve the flow of traffic at intersections, leading to the future possibility of controlling several connected intersections in a distributed way

Reliability models for dataflow computer systems

The demands for concurrent operation within a computer system and the representation of parallelism in programming languages have yielded a new form of program representation known as data flow (DENN 74, DENN 75, TREL 82a). A new model based on data flow principles for parallel computations and parallel computer systems is presented. Necessary conditions for liveness and deadlock freeness in data flow graphs are derived. The data flow graph is used as a model to represent asynchronous concurrent computer architectures including data flow computers

Formal and Informal Methods for Multi-Core Design Space Exploration

We propose a tool-supported methodology for design-space exploration for embedded systems. It provides means to define high-level models of applications and multi-processor architectures and evaluate the performance of different deployment (mapping, scheduling) strategies while taking uncertainty into account. We argue that this extension of the scope of formal verification is important for the viability of the domain.Comment: In Proceedings QAPL 2014, arXiv:1406.156