Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

On the Efficiency of Multi-Source Energy Harvesters

Energy harvesters can be used to provide small amounts of power in remote locations. Applications include powering wireless sensor networks and powering microelectromechanical systems. A wealth of different designs exists for harvesting energy from different sources, including designs which harvest from multiple sources simultaneously. However, there are no universally accepted metrics for assessing the performance of energy harvesters; this can make it impossible to compare designs in any meaningful way. The first part of this thesis develops a domain-neutral framework for describing and analysing the behaviour of energy harvesters. This involves introducing a system of dimensionally consistent analogies into energy harvesting. Using this domain-neutral and dimensionally consistent framework, it is possible to come up with general expressions for the behaviour of single-source energy harvesting systems. This approach is then validated experimentally for single-source energy harvesters. The second part of this thesis involves extending the theoretical analysis to multi-source energy harvesters. Using the system of analogies defined in the first part of the thesis it is possible to create an n-degree-of-freedom matrix representation of a multi-source energy harvester. This enables us to derive expressions which are valid for both single-source and multi-source energy harvesters. The expressions for the maximum power absorbed by an energy harvesting device are shown to be independent of the number of sources, as well as any static coupling or coupling through material effects (e.g. piezoelectric). Numerical simulations are used to explore the validity of these expressions for various system configurations driven with a mixed stochastic-deterministic input signal. From the results of these numerical simulations, a practical approach for estimating the efficiency of an energy harvester using the maximum power absorbed as a theoretical limit is described. The third part of this thesis describes experiments which validate the theoretical analysis. These experiments are used to provide an example of how to calculate and compare the efficiency of energy harvesting designs

CMOS and SOI CMOS FET-based gas sensors

In recent years, there has been considerable interest in the use of gas/vapour monitors and electronic nose instruments by the environmental, automotive and medical industries. These applications require low cost and low power sensors with high yield and high reproducibility, with an annual prospective market of 1 million pounds. Present device and sensor technologies suffer a major limitation, their incompatibility with a standard silicon CMOS process. These technologies have either operating/annealing temperatures unsuited for MOSFET operation or an inappropriate sensing mechanism. The aim of this research is the development of CMOS compatible gas/vapour sensors, with a low cost of fabrication, high device repeatability and, in the future, transducer sensor amalgamation. Two novel approaches have been applied, utilising bulk CMOS and SOI BiCMOS. The bulk CMOS designs use a MOSFET sensing structure, with an active polymeric gate material, operating at low temperatures (<100°C), based on an array device of four elements, with channel lengths of 10 μm or 5 μm. The SOI designs exploit a MOSFET heater with a chemoresistive or chemFET sensing structure, on a thin membrane formed by the epi-taxial layer. By applying SOI technology, the first use in gas sensor applications, operating temperatures of up to 300 °C can be achieved at a power cost of only 35 mW (simulated). Full characterisation of the bulk CMOS chemFET sensors has been performed using electrochemically deposited (e.g. poly(pyrrole)/BSA)) and composite polymers (e.g. poly(9-vinylcarbazole)) to ethanol and toluene vapour in air. In addition, environmental factors (humidity and temperature) on the response and baseline were investigated. This was carried out using a newly developed flow injection analysis test station, which conditions the test vapour to precise analyte (<15 PPM of toluene) and water concentrations at a fixed temperature (RT to 105°C +- 0.1), with the sensor characterised by either I-V or constant current instrumentation. N-channel chemFET sensors operated at constant current (10 μA) with electrochemically deposited and composite polymers showed sensitivities of up to 1.1 μV/PPM and 4.0 μV/PPM to toluene vapour and to 1.1 μV/PPM and 0.4 μV/PPM for ethanol vapour, respectively, with detection limits of <20 PPM and <100 PPM to toluene and <20 PPM and 10+ PPM to ethanol vapour (limited by baseline noise), respectively. These responses followed either a power law (composite polymers) or a modified Langmuir isotherm model (electrochemically deposited polymers) with analyte concentration. It is proposed that this reaction-rate limited response is due to an alteration in polymers work function by either a partial charge transfer from the analyte or a swelling effect (polymer expansion). Increasing humidity caused, in nearly all cases a reduction in relative baseline, possible by dipole formation at the gate oxide surface. For the response, increasing humidity had no effect on sensors with composite polymers and an increase for sensors with electrochemically-deposited polymers. Higher temperatures caused a reduction in baseline signal, by a thermal expansion of the polymer, and a reduction in response explained by the analyte boiling point model describing a reduction in the bulk solubility of the polymer. Electrical and thermal characterisation of the SOI heaters, fabricated by the MATRA process, has been performed. I-V measurements show a reduction in drain current for a MOSFET after back-etching, by a degradation of the carrier mobility. Dynamic measurement showed a two stage thermal response (dual exponential), as the membrane reaching equilibrium (100-200 ms) followed by the bulk (1-2 s). A temperature coefficient of 8 mW/°C was measured, this was significantly higher than expected from simulations, explained by the membrane being only partially formed. Diode and resistive temperature sensors showed detection limits under 0.1°C and shown to measure a modulated heater output of less than 1°C at frequencies higher than 10Hz. The principal research objectives have been achieved, although further work on the SOI device is required. The results and theories presented in this study should provide a useful contribution to this research area

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Monolithic electronic-photonic integration in state-of-the-art CMOS processes

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 388-407).As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. Photonic devices promise to break this bottleneck with superior bandwidth-density and energy-efficiency. Initial work by many research groups to adapt photonic device designs to a silicon-based material platform demonstrated suitable independent performance for such links. However, electronic-photonic integration attempts to date have been limited by the high cost and complexity associated with modifying CMOS platforms suitable for modern high-performance computing applications. In this work, we instead utilize existing state-of-the-art electronic CMOS processes to fabricate integrated photonics by: modifying designs to match the existing process; preparing a design-rule compliant layout within industry-standard CAD tools; and locally-removing the handle silicon substrate in the photonic region through post-processing. This effort has resulted in the fabrication of seven test chips from two major foundries in 28, 45, 65 and 90 nm CMOS processes. Of these efforts, a single die fabricated through a widely available 45nm SOI-CMOS mask-share foundry with integrated waveguides with 3.7 dB/cm propagation loss alongside unmodified electronics with less than 5 ps inverter stage delay serves as a proof-of-concept for this approach. Demonstrated photonic devices include high-extinction carrier-injection modulators, 8-channel wavelength division multiplexing filter banks and low-efficiency silicon germanium photodetectors. Simultaneous electronic-photonic functionality is verified by recording a 600 Mb/s eye diagram from a resonant modulator driven by integrated digital circuits. Initial work towards photonic device integration within the peripheral CMOS flow of a memory process that has resulted in polysilicon waveguide propagation losses of 6.4 dB/cm will also be presented.by Jason S. Orcutt.Ph.D

Chemical vapor deposition of thin films for ULSI interconnect metallization

We have studied the kinetics of copper chemical vapor deposition (CVD) for interconnect metallization using solution delivery of Cu(hfac)2 (Cu(II) hexafluoroacetyl-acetonate) dissolved in isopropanol. We observe a growth rate of 17.7 „b 1.5 nm/min at reference conditions of 300„aC substrate temperature, 0.025 Torr Cu(hfac)2 partial pressure, 1.6 Torr isopropanol (reducing agent), and 80 Torr H2 (carrier gas). The film resistivity approaches the bulk value of copper for film thickness greater than 100 nm. Reaction order experiments show first-order kinetics with respect to Cu(hfac)2 partial pressure and zero-order with respect to isopropanol. A series reaction mechanism including three kinetically significant steps (adsorption of Cu(hfac)2, dissociation of (hfac) ligand, and desorption of (hfac)) is used to describe the observed kinetic results. The proposed rate determining step is the dissociation of (hfac) ligand when the pressure ratio of Cu(hfac)2 to isopropanol is low, and becomes the desorption of (hfac) when the pressure ratio is high. We also examined a low temperature chemical vapor deposition process for the growth of tantalum thin films using SiH4 reduction of TaF5. Using a temperature of 350„aC and reactant partial pressures of 0.2 Torr TaF5 and 0.3 Torr SiH4, we obtain a growth rate of 2.2 ¡Ó 1.7 nm/min. The XPS analysis results show that the Ta film is Si free, but contains relatively high oxygen concentration because of residual gas contamination. Lastly, we have studied a batch CVD process for palladium seed layer deposition using H2 reduction of Pd(hfac)2 (Pd(II) hexafluoroacetylacetonate). Nano-sized Pd particles with nuclei density between 1 to 14 clusters/ƒÝm2 are observed using AFM. The quality of the Pd seed layer is examined by depositing electroless copper film. We have investigated the influence of CVD operating conditions (deposition time, activation temperature, and precursor concentration) on the activity of the Pd seed layers (i.e., by monitoring visual appearance and deposition rates of the ELD Cu films). At the optimized conditions we can deposit uniform Cu films at a rate of 3.4 „b 1.4 nm/s. Additional work is needed to improve the resistivity and adhesion of the films

Engineering handbook

2006 handbook for the faculty of Engineerin