Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Characterization of optical interconnects

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.Includes bibliographical references (p. 72-75).Interconnect has become a major issue in deep sub-micron technology. Even with copper and low-k dielectrics, parasitic effects of interconnects will eventually impede advances in integrated electronics. One technique that has the potential to provide a paradigm shift is optics. This project evaluates the feasibility of optical interconnects for distributing data and clock signals. In adopting this scheme, variation is introduced by the detector, the waveguides, and the optoelectronic circuit, which includes device, power supply and temperature variations. We attempt to characterize the effects of the aforementioned sources of variation by designing a baseline optoelectronic circuitry and fabricating a test chip which consists of the circuitry and detectors. Simulations are also performed to supplement the effort. The results are compared with the performance of traditional metal interconnects. The feasibility of optical interconnects is found to be sensitive to the optoelectronic circuitry used. Variation effects from the devices and operating conditions have profound impact on the performance of optical interconnects since they introduce substantial skew and delay in the otherwise ideal system.by Shiou Lin Sam.S.M

An Implantable Low Pressure Biosensor Transponder

The human body’s intracranial pressure (ICP) is a critical element in sustaining healthy blood flow to the brain while allowing adequate volume for brain tissue within the relatively rigid structure of the cranium. Disruptions in the body’s maintenance of intracranial pressure are often caused by hemorrhage, tumors, edema, or excess cerebral spinal fluid resulting in treatments that are estimated to globally cost up to approximately five billion dollars annually. A critical element in the contemporary management of acute head injury, intracranial hemorrhage, stroke, or other conditions resulting in intracranial hypertension, is the real-time monitoring of ICP. Currently such monitoring can only take place short-term within an acute care hospital, is prone to measurement drift, and is comprised of externally tethered pressure sensors that are temporarily implanted into the brain, thus carrying a significant risk of infection. To date, reliable, low drift, completely internalized, long-term ICP monitoring devices remain elusive. In addition to being safer and more reliable in the short-term, such a device would expand the use of ICP monitoring for the management of chronic diseases involving ICP hypertension and further expand research into these disorders. This research studies the current challenges of existing ICP monitoring systems and investigates opportunities for potentially allowing long-term implantable bio-pressure sensing, facilitating possible improvements in treatment strategies. Based upon the research, this thesis evaluates piezo-resistive strain sensing for low power, sub-millimeter of mercury resolution, in application to implantable intracranial pressure sensing

Development and Analysis of Non-Delay-Line Constant-Fraction Discriminator Timing Circuits, Including a Fully-Monolithic CMOS Implementation

A constant-fraction discriminator (CFD) is a time pick-off circuit providing time derivation that is insensitive to input-signal amplitude and, in some cases, input-signal rise time. CFD time pick-off circuits are useful in Positron Emission Tomography (PET) systems where Bismuth Germanate (BGO)/photomultiplier scintillation detectors detect coincident, 511-keV annihilation gamma rays. Time walk and noise-induced timing jitter in time pick-off circuits are discussed along with optimal and sub-optimal timing filters designed to minimize timing jitter. Additionally, the effects of scintillation-detector statistics on timing performance are discussed, and Monte Carlo analysis is developed to provide estimated timing and energy spectra for selected detector and time pick-off circuit configurations. The traditional delay-line CFD is then described with a discussion of deterministic (non statistical) performance and statistical Monte Carlo timing performance. A new class of non-delay-line CFD circuits utilizing lowpass- and/or allpass-filter delay-line approximations is then presented. The timing performance of these non-delay-line CFD circuits is shown to be comparable to traditional delay-line CFD circuits. Following the development and analysis of non-delay-line CFD circuits, a fully-monolithic, non-delay-line CFD circuit is presented which was fabricated in a standard digital, 2-μ, double-meta], double-poly, n-well CMOS process. The CMOS circuits developed include a low time walk comparator having a time walk of approximately 175 ps for input signals with amplitudes between 10-mV to 2000-mV and a rise time (10 - 90%) of 10 ns. Additionally, a fifth-order, continuous-time filter having a bandwidth of over 100 MHz was developed to provide CFD signal shaping without a delay line. The measured timing resolution (3.26 ns FWITh1, 6.50 ns FWTM) of the fully-monolithic, CMOS CFD is comparable to measured resolution (3.30 ns FWHM, 6.40 ns FWTM) of a commercial, discrete, bipolar CFD containing an external delay line. Each CFD was tested with a PET EGO/photomultiplier scintillation detector and a preamplifier having a 10-ns (10 - 90%) rise-time. The development of a fully-monolithic, CMOS CFD circuit, believed to be the first such reported development, is significant for PET and other systems that employ many front-end CFD time pick-off circuits

Detectors for the James Webb Space Telescope Near-Infrared Spectrograph I: Readout Mode, Noise Model, and Calibration Considerations

We describe how the James Webb Space Telescope (JWST) Near-Infrared Spectrograph's (NIRSpec's) detectors will be read out, and present a model of how noise scales with the number of multiple non-destructive reads sampling-up-the-ramp. We believe that this noise model, which is validated using real and simulated test data, is applicable to most astronomical near-infrared instruments. We describe some non-ideal behaviors that have been observed in engineering grade NIRSpec detectors, and demonstrate that they are unlikely to affect NIRSpec sensitivity, operations, or calibration. These include a HAWAII-2RG reset anomaly and random telegraph noise (RTN). Using real test data, we show that the reset anomaly is: (1) very nearly noiseless and (2) can be easily calibrated out. Likewise, we show that large-amplitude RTN affects only a small and fixed population of pixels. It can therefore be tracked using standard pixel operability maps.Comment: 55 pages, 10 figure

Negative Bias Temperature Instability (NBTI) Monitoring and Mitigation Technique for MOSFET

修士論

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

Characterization of a Single Photon Sensing and Photon Number Resolving CMOS Detector for Astrophysics

Next-generation NASA missions, such as the LUVIOR and HabEx concepts, require single photon counting large-format detectors. Charge Coupled Devices (CCDs) have typically been used for optical applications in similar flagship missions of the past. CCDs have excellent properties in most metrics but have their own challenges for single photon counting applications. First, typical CCDs have a read noise of a few electrons, although recent modifications (EMCCDs) use an on-chip gain to amplify the signal above the read noise. Secondly, the signal is carried by charge that is transferred across the detector array. While CCDs for NASA missions are carefully fabricated to minimize defects, continuous bombardment from high energy radiation in space will damage the detector over the lifetime of the mission. This will degrade the charge transfer efficiency and in turn, reduce the single photon counting ability of the CCD. CMOS devices offer a different architecture that mitigates some of these problems. In CMOS image sensors, each pixel has its own charge to voltage converter and in-pixel amplifier mitigating issues found with charge transfer efficiency. Additional circuits that are critical to operation of the sensor can be incorporated on chip allowing for a parallel readout architecture that increases frame rate and can decrease read noise. This thesis is a collection of work for the characterization of a room temperature characterization, low-noise, single photon counting and photon number resolving CMOS detector. The work performed in this thesis will provide the framework for a technology development project funded by NASA Cosmic Origins (COR) program office. At the end of the two-year project, a megapixel CMOS focal plane array will be demonstrated to satisfy the stated needs of the LUVOIR and HabEx future astrophysics space mission concepts with a launch date near the 2040s

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Statistical modelling of nano CMOS transistors with surface potential compact model PSP

The development of a statistical compact model strategy for nano-scale CMOS transistors is presented in this thesis. Statistical variability which arises from the discreteness of charge and granularity of matter plays an important role in scaling of nano CMOS transistors especially in sub 50nm technology nodes. In order to achieve reasonable performance and yield in contemporary CMOS designs, the statistical variability that affects the circuit/system performance and yield must be accurately represented by the industry standard compact models. As a starting point, predictive 3D simulation of an ensemble of 1000 microscopically different 35nm gate length transistors is carried out to characterize the impact of statistical variability on the device characteristics. PSP, an advanced surface potential compact model that is selected as the next generation industry standard compact model, is targeted in this study. There are two challenges in development of a statistical compact model strategy. The first challenge is related to the selection of a small subset of statistical compact model parameters from the large number of compact model parameters. We propose a strategy to select 7 parameters from PSP to capture the impact of statistical variability on current-voltage characteristics. These 7 parameters are used in statistical parameter extraction with an average RMS error of less than 2.5% crossing the whole operation region of the simulated transistors. Moreover, the accuracy of statistical compact model extraction strategy in reproducing the MOSFET electrical figures of merit is studied in detail. The results of the statistical compact model extraction are used for statistical circuit simulation of a CMOS inverter under different input-output conditions and different number of statistical parameters. The second challenge in the development of statistical compact model strategy is associated with statistical generation of parameters preserving the distribution and correlation of the directly extracted parameters. By using advanced statistical methods such as principal component analysis and nonlinear power method, the accuracy of parameter generation is evaluated and compared to directly extracted parameter sets. Finally, an extension of the PSP statistical compact model strategy to different channel width/length devices is presented. The statistical trends of parameters and figures of merit versus channel width/length are characterized