151 research outputs found

    Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

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    This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

    Scaling and intrinsic parameter fluctuations in nanoCMOS devices

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    The core of this thesis is a thorough investigation of the scaling properties of conventional nano-CMOS MOSFETs, their physical and operational limitations and intrinsic parameter fluctuations. To support this investigation a well calibrated 35 nm physical gate length real MOSFET fabricated by Toshiba was used as a reference transistor. Prior to the start of scaling to shorter channel lengths, the simulators were calibrated against the experimentally measured characteristics of the reference device. Comprehensive numerical simulators were then used for designing the next five generations of transistors that correspond to the technology nodes of the latest International Technology Roadmap for Semiconductors (lTRS). The scaling of field effect transistors is one of the most widely studied concepts in semiconductor technology. The emphases of such studies have varied over the years, being dictated by the dominant issues faced by the microelectronics industry. The research presented in this thesis is focused on the present state of the scaling of conventional MOSFETs and its projections during the next 15 years. The electrical properties of conventional MOSFETs; threshold voltage (VT), subthreshold slope (S) and on-off currents (lon, Ioffi ), which are scaled to channel lengths of 35, 25, 18, 13, and 9 nm have been investigated. In addition, the channel doping profile and the corresponding carrier mobility in each generation of transistors have also been studied and compared. The concern of limited solid solubility of dopants in silicon is also addressed along with the problem of high channel doping concentrations in scaled devices. The other important issue associated with the scaling of conventional MOSFETs are the intrinsic parameter fluctuations (IPF) due to discrete random dopants in the inversion layer and the effects of gate Line Edge Roughness (LER). The variations of the three important MOSFET parameters (loff, VT and Ion), induced by random discrete dopants and LER have been comprehensively studied in the thesis. Finally, one of the promising emerging CMOS transistor architectures, the Ultra Thin Body (UTB) SOl MOSFET, which is expected to replace the conventional MOSFET, has been investigated from the scaling point of view

    Gate leakage variability in nano-CMOS transistors

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    Gate leakage variability in nano-scale CMOS devices is investigated through advanced modelling and simulations of planar, bulk-type MOSFETs. The motivation for the work stems from the two of the most challenging issues in front of the semiconductor industry - excessive leakage power, and device variability - both being brought about with the aggressive downscaling of device dimensions to the nanometer scale. The aim is to deliver a comprehensive tool for the assessment of gate leakage variability in realistic nano-scale CMOS transistors. We adopt a 3D drift-diffusion device simulation approach with density-gradient quantum corrections, as the most established framework for the study of device variability. The simulator is first extended to model the direct tunnelling of electrons through the gate dielectric, by means of an improved WKB approximation. A study of a 25 nm square gate n-type MOSFET demonstrates that combined effect of discrete random dopants and oxide thickness variation lead to starndard deviation of up to 50% (10%) of the mean gate leakage current in OFF(ON)-state of the transistor. There is also a 5 to 6 times increase of the magnitude of the gate current, compared to that simulated of a uniform device. A significant part of the research is dedicated to the analysis of the non-abrupt bandgap and permittivity transition at the Si/SiO2 interface. One dimensional simulation of a MOS inversion layer with a 1nm SiO2 insulator and realistic band-gap transition reveals a strong impact on subband quantisation (over 50mV reduction in the delta-valley splitting and over 20% redistribution of carriers from the delta-2 to the delta-4 valleys), and enhancement of capacitance (over 10%) and leakage (about 10 times), relative to simulations with an abrupt band-edge transition at the interface

    Scaling and variability in ultra thin body silicon on insulator (UTB SOI) MOSFETs

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    The main objective of this thesis is to perform a comprehensive simulation study of the statistical variability in well scaled fully depleted ultra thin body silicon on insulator (FD-UTB SOI) at nanometer regime. It describes the design procedure for template FDUTB SOI transistor scaling and the impacts of statistical variability and reliability the scaled template transistor. The starting point of this study is a systematic simulation analysis based on a welldesigned 32nm thin body SOI template transistor provided by the FP7 project PULLNANO. The 32nm template transistor is consistent with the International Technology Roadmap for Semiconductor (ITRS) 2009 specifications. The wellestablished 3D ‘atomistic’ simulator GARAND has been employed in the designing of the scaled transistors and to carry out the statistical variability simulations. Following the foundation work in characterizing and optimizing the template 32 nm gate length transistor, the scaling proceeds down to 22 nm, 16 nm and 11 nm gate lengths using typically 0.7 scaling factor in respect of the horizontal and vertical transistor dimensions. The device design process is targeted for low power applications with a careful consideration of the impacts of the design parameters choice including buried oxide thickness (TBOX), source/drain doping abruptness (σ) and spacer length (Lspa). In order to determine the values of TBOX, σ, and Lspa, it is important to analyze simulation results, carefully assessing the impact on manufacturability and to consider the corresponding trade-off between short channel effects and on-current performance. Considering the above factors, TBOX = 10nm, σ = 2nm/dec and Lspa = 7nm have been adopted as optimum values respectively. iv The statistical variability of the transistor characteristics due to intrinsic parameter fluctuation (IPF) in well-scaled FD-UTB SOI devices is systematically studied for the first time. The impact of random dopant fluctuation (RDF), line edge roughness (LER) and metal gate granularity (MGG) on threshold voltage (Vth), on-current (Ion) and drain induced barrier lowering (DIBL) are analysed. Each principal sources of variability is treated individually and in combination with other variability sources in the simulation of large ensembles of microscopically different devices. The introduction of highk/ metal gate stack has improved the electrostatic integrity and enhanced the overall device performance. However, in the case of fully depleted channel transistors, MGG has become a dominant variability factor for all critical electrical parameters at gate first technology. For instance, σVth due to MGG increased to 41.9 mV at 11nm gate length compared to 26.0 mV at 22nm gate length. Similar trend has also been observed in σIon, increasing from 0.065 up to 0.174 mA/ÎŒm when the gate length is reduced from 22 nm down to 11 nm. Both RDF and LER have significant role in the intrinsic parameter fluctuations and therefore, none of these sources should be overlooked in the simulations. Finally, the impact of different variability sources in combination with positive bias temperature instability (PBTI) degradation on Vth, Ion and DIBL of the scaled nMOSFETs is investigated. Our study indicates that BTI induced charge trapping is a crucial reliability problem for the FD-UTB SOI transistors operation. Its impact not only introduces a significant degradation of transistor performance, but also accelerates the statistical variability. For example, the effect of a late degradation stage (at trap density of 1e12/cm2) in the presence of RDF, LER and MGG results in σVth increase to 36.9 mV, 45.0 mV and 58.3 mV for 22 nm, 16 nm and 11 nm respectively from the original 29.0 mV, 37.9 mV and 50.4 mV values in the fresh transistors

    3D drift diffusion and 3D Monte Carlo simulation of on-current variability due to random dopants

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    In this work Random Discrete Dopant induced on-current variations have been studied using the Glasgow 3D atomistic drift/diffusion simulator and Monte Carlo simulations. A methodology for incorporating quantum corrections into self-consistent atomistic Monte Carlo simulations via the density gradient effective potential is presented. Quantum corrections based on the density gradient formalism are used to simultaneously capture quantum confinement effects. The quantum corrections not only capture charge confinement effects, but accurately represent the electron impurity interaction used in previous \textit{ab initio} atomistic MC simulations, showing agreement with bulk mobility simulation. The effect of quantum corrected transport variation in statistical atomistic MC simulation is then investigated using a series of realistic scaled devices nMOSFETs transistors with channel lengths 35 nm, 25 nm, 18nm, 13 nm and 9 nm. Such simulations result in an increased drain current variability when compared with drift diffusion simulation. The comprehensive statistical analysis of drain current variations is presented separately for each scaled transistor. The investigation has shown increased current variation compared with quantum corrected drift diffusion simulation and with previous classical MC results. Furthermore, it has been studied consistently the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano CMOS transistors. For the first time, a hierarchic simulation strategy to accurately transfer the increased on-current variability obtained from the ‘ab initio’ MC simulations to DD simulations is subsequently presented. The MC corrected DD simulations are used to produce target ID−VGI_D-V_G characteristics from which statistical compact models are extracted for use in preliminary design kits at the early stage of new technology development. The impact of transport variability on the accuracy of delay simulation are investigated in detail. Accurate compact models extraction methodology transferring results from accurate physical variability simulation into statistical compact models suitable for statistical circuit simulation is presented. In order to examine te size of this effect on circuits Monte Carlo SPICE simulations of inverter were carried out for 100 samples

    Miniaturized Transistors, Volume II

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    In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

    Analysis on Supercapacitor Assisted Low Dropout (SCALDO) Regulators

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    State-of-the-art electronic systems employ three fundamental techniques for DC-DC converters: (a) switch-mode power supplies (SMPS); (b) linear power supplies; (c) switched capacitor (charge pump) converters. In practical systems, these three techniques are mixed to provide a complex, but elegant, overall solution, with energy efficiency, effective PCB footprint, noise and transient performance to suit different electronic circuit blocks. Switching regulators have relatively high end-to-end efficiency, in the range of 70 to 93%, but can have issues with output noise and EMI/RFI emissions. Switched capacitor converters use a set of capacitors for energy storage and conversion. In general, linear regulators have low efficiencies in the range 30 to 60%. However, they have outstanding output characteristics such as low noise, excellent transient response to load current fluctuations, design simplicity and low cost design which are far superior to SMPS. Given the complex situation in switch-mode converters, low dropout (LDO) regulators were introduced to address the equirements of noise-sensitive and fast transient loads in portable devices. A typical commercial off-the-shelf LDO has its input voltage slightly higher than the desired regulated output for optimal efficiency. The approximate efficiency of a linear regulator, if the power consumed by the control circuits is negligible, can be expressed by the ratio of Vo/Vin. A very low frequency supercapacitor circulation technique can be combined with commercial low dropout regulator ICs to significantly increase the end-to-end efficiency by a multiplication factor in the range of 1.33 to 3, compared to the efficiency of a linear regulator circuit with the same input-output voltages. In this patented supercapacitor-assisted low dropout (SCALDO) regulator technique developed by a research team at the University of Waikato, supercapacitors are used as lossless voltage droppers, and the energy reuse occurs at very low frequencies in the range of less than ten hertz, eliminating RFI/EMI concerns. This SCALDO technique opens up a new approach to design step-down, DC-DC converters suitable for processor power supplies with very high end-to-end efficiency which is closer to the efficiencies of practical switching regulators, while maintaining the superior output specifications of a linear design. Furthermore, it is important to emphasize that the SCALDO technique is not a variation of well-known switched capacitor DC-DC converters. In this thesis, the basic SCALDO concept is further developed to achieve generalised topologies, with the relevant theory that can be applied to a converter with any input-output step-down voltage combination. For these generalised topologies, some important design parameters, such as the number of supercapacitors, switching matrix details and efficiency improvement factors, are derived to form the basis of designing SCALDO regulators. With the availability of commercial LDO ICs with output current ratings up to 10 A, and thin-prole supercapacitors with DC voltage ratings from 2.3 to 5.5 V, several practically useful, medium-current SCALDO prototypes: 12V-to-5V, 5V-to-2V, 5.5V-to-3.3V have been developed. Experimental studies were carried out on these SCALDO prototypes to quantify performance in terms of line regulation, load regulation, efficiency and transient response. In order to accurately predict the performance and associated waveforms of the individual phases (charge, discharge and transition) of the SCALDO regulator, Laplace transform-based theory for supercapacitor circulation is developed, and analytical predictions are compared with experimental measurements for a 12V-to-5V prototype. The analytical results tallied well with the practical waveforms observed in a 12V-to-5V converter, indicating that the SCALDO technique can be generalized to other versatile configurations, and confirming that the simplified assumptions used to describe the circuit elements are reasonable and justifiable. After analysing the performance of several SCALDO prototypes, some practical issues in designing SCALDO regulators have been identified. These relate to power losses and implications for future development of the SCALDO design

    Strain-Engineered MOSFETs

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    This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization
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