Modeling and Simulation of Subthreshold Characteristics of Short-Channel Fully-Depleted Recessed-Source/Drain SOI MOSFETs

Non-conventional metal-oxide-semiconductor (MOS) devices have attracted researchers‟ attention for future ultra-large-scale-integration (ULSI) applications since the channel length of conventional MOS devices approached the physical limit. Among the non-conventional CMOS devices which are currently being pursued for the future ULSI, the fully-depleted (FD) SOI MOSFET is a serious contender as the SOI MOSFETs possess some unique features such as enhanced short-channel effects immunity, low substrate leakage current, and compatibility with the planar CMOS technology. However, due to the ultra-thin source and drain regions, FD SOI MOSFETs possess large series resistance which leads to the poor current drive capability of the device despite having excellent short-channel characteristics. To overcome this large series resistance problem, the source/drain area may be increased by extending S/D either upward or downward. Hence, elevated-source/drain (E-S/D) and recessed-source/drain (Re-S/D) are the two structures which can be used to minimize the series resistance problem. Due to the undesirable issues such as parasitic capacitance, current crowding effects, etc. with E-S/D structure, the Re-S/D structure is a better choice. The FD Re-S/D SOI MOSFET may be an attractive option for sub-45nm regime because of its low parasitic capacitances, reduced series resistance, high drive current, very high switching speed and compatibility with the planar CMOS technology. The present dissertation is to deal with the theoretical modeling and computer-based simulation of the FD SOI MOSFETs in general, and recessed source/drain (Re-S/D) ultra-thin-body (UTB) SOI MOSFETs in particular. The current drive capability of Re-S/D UTB SOI MOSFETs can be further improved by adopting the dual-metal-gate (DMG) structure in place of the conventional single-metal-gate-structure. However, it will be interesting to see how the presence of two metals as gate contact changes the subthreshold characteristics of the device. Hence, the effects of adopting DMG structure on the threshold voltage, subthreshold swing and leakage current of Re-S/D UTB SOI MOSFETs have been studied in this dissertation. Further, high-k dielectric materials are used in ultra-scaled MOS devices in order to cut down the quantum mechanical tunneling of carriers. However, a physically thick gate dielectric causes fringing field induced performance degradation. Therefore, the impact of high-k dielectric materials on subthreshold characteristics of Re-S/D SOI MOSFETs needs to be investigated. In this dissertation, various subthreshold characteristics of the device with high-k gate dielectric and metal gate electrode have been investigated in detail. Moreover, considering the variability problem of threshold voltage in ultra-scaled devices, the presence of a back-gate bias voltage may be useful for ultimate tuning of the threshold voltage and other characteristics. Hence, the impact of back-gate bias on the important subthreshold characteristics such as threshold voltage, subthreshold swing and leakage currents of Re-S/D UTB SOI MOSFETs has been thoroughly analyzed in this dissertation. The validity of the analytical models are verified by comparing model results with the numerical simulation results obtained from ATLAS™, a device simulator from SILVACO Inc

Impact of intrinsic parameter fluctuations in ultra-thin body silicon-on-insulator MOSFET on 6-transistor SRAM cell

As CMOS device dimensions are being aggressively scaled, the device characteristic must be assessed against fundamental physical limits. Nanoscale device modelling and statistical circuit analysis is needed to provide designer with ability to explore innovative new MOSFET devices as well as understanding the limits of the scaling process. This work introduces a systematic simulation methodology to investigate the impact of intrinsic parameter fluctuation for a novel Ultra-Thin-Body (UTB) Silicon-on-Insulator (SOI) transistor on the corresponding device and circuits. It provides essential link between physical device-level numerical simulation and circuit-level simulation. A systematic analysis of the effects of random discrete dopants, body thickness variations and line edge roughness on a well scaled 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFET is performed. To fully realise the performance benefits of UTB-SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuations information into the compact model is developed. The impact of intrinsic parameter fluctuations on the stability and performance of 6T SRAM has been investigated. A comparison with the behaviour of a 6T SRAM based on a conventional 35 nm MOSFET is also presented

Compact modeling of the rf and noise behavior of multiple-gate mosfets

La reducción de la tecnología MOSFET planar ha sido la opción tecnológica dominante en las últimas décadas. Sin embargo, hemos llegado a un punto en el que los materiales y problemas en los dispositivos surgen, abriendo la puerta para estructuras alternativas de los dispositivos. Entre estas estructuras se encuentran los dispositivos DG, SGT y Triple-Gate. Estas tres estructuras están estudiadas en esta tesis, en el contexto de rducir las dimensiones de los dispositivos a tamaños tales que los mecanismos cuánticos y efectos de calan coro deben tenerse n cuenta. Estos efectos vienen con una seria de desafíos desde el pun to de vista de modelación, unos de los más grandes siendo el tiempo y los recursos comprometidos para ejecutar las simulaciones. para resolver este problema, esta tesis propone modelos comlets analíticos y compactos para cada una de las geometrías, validos desde DC hasta el modo de operación en Rf para los nodos tecnológicos futuros. Dichos modelos se han extendido para analizar el ruido de alta frecuencia en estos diapositivos

DESIGN, COMPACT MODELING AND CHARACTERIZATION OF NANOSCALE DEVICES

Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics

ATLAS simulation based characterization of Recessed-S/D FD SOI MOSFETs with non-uniform lateral doping

As scaling down the technology into nanometer regime, short channel effects (SCE) and manufacturing limits will increase, which alters the performance of devices. Silicon-on-insulator (SOI) has got reputation that is a promising technology in the last decade offering more CMOS devices with higher density, higher speed, and reduced second order effects for submicron VLSI applications. Recent investigations have been reported fully depleted (FD) SOI devices are the best solutions because of their suitability to shrinking methods comparative to bulk silicon CMOS devices. Further, implicit the extra advantages, like sub threshold current reduction and improvement in Analog/RF performance; channel engineering and source/drain engineering techniques are implemented in FD SOI MOSFET. Recessed FD SOI MOSFET with non-uniform lateral doping structure gives some solutions to SCEs and better device performance by changing doping levels in different length ratios of channel region in lateral direction In this project work, a comprehensive performance study of source/drain (S/D) engineered SOI MOSFET with non-uniform doping in Channel region is presented. To analyse the characterisation of proposed structure, all the characteristics parameters extracted by using simulation tool. Those characteristics parameters are Surface potential, Threshold voltage, Sub-threshold current, Device capacitances, Drain current, Transconductance, Output conductance, Transconductance generation efficiency, Cut-off frequency and Maximum frequency of oscillation have been carried out and compared with its SOI MOSFETs and non-S/D engineered ones. To extract the characteristics parameters of Device H and Y-parameters are used. All these numerical simulation results are performed using ATLASTM, a 2-D numerical device simulator from SILVACO Inc

Monte Carlo study of current variability in UTB SOI DG MOSFETs

The scaling of conventional silicon based MOSFETs is increasingly difficult into the nanometer regime due to short channel effects, tunneling and subthreshold leakage current. Ultra-thin body silicon-on-insulator based architectures offer a promising alternative, alleviating these problems through their geometry. However, the transport behaviour in these devices is more complex, especially for silicon thicknesses below 10 nm, with enhancement from band splitting and volume inversion competing with scattering from phonons, Coulomb interactions, interface roughness and body thickness fluctuation. Here, the effect of the last scattering mechanism on the drive current is examined as it is considered a significant limitation to device performance for body thicknesses below 5 nm. A simulation technique that properly captures non-equilibrium transport, includes quantum effects and maintains computational efficiency is essential for the study of this scattering mechanism. Therefore, a 3D Monte Carlo simulator has been developed which includes this scattering effect in an ab initio fashion, and quantum corrections using the Density Gradient formalism. Monte Carlo simulations using `frozen field' approximation have been carried out to examine the dependence of mobility on silicon thickness in large, self averaging devices. This approximation is then used to carry out statistical studies of uniquely different devices to examine the variability of on-current. Finally, Monte Carlo simulations self consistent with Poisson's equation have been carried out to further investigate this mechanism