1,843 research outputs found

    Linearization of The Timing Analysis and Optimization of Level-Sensitive Circuits

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    This thesis describes a linear programming (LP) formulation applicable to the static timing analysis of large scale synchronous circuits with level-sensitive latches. The automatic timing analysis procedure presented here is composed of deriving the connectivity information, constructing the LP model and solving the clock period minimization problem of synchronous digital VLSI circuits. In synchronous circuits with level-sensitive latches, operation at a reduced clock period (higher clock frequency) is possible by takingadvantage of both non-zero clock skew scheduling and time borrowing. Clock skew schedulingis performed in order to exploit the benefits of nonidentical clock signal delays on circuit timing. The time borrowing property of level-sensitive circuits permits higher operating frequencies compared to edge-sensitivecircuits. Considering time borrowing in the timing analysis, however, introduces non-linearity in this timing analysis. The modified big M (MBM) method is defined in order to transform the non-linear constraints arising in the problem formulation into solvable linear constraints. Equivalent LP model problemsfor single-phase clock synchronization of the ISCAS'89 benchmark circuits are generated and these problems are solved by the industrial LP solver CPLEX. Through the simultaneous application of time borrowing and clock skew scheduling, up to 63% improvements are demonstrated in minimum clock period with respect to zero-skew edge-sensitive synchronous circuits. The timing constraints governing thelevel-sensitive synchronous circuit operation not only solve the clock period minimization problem but also provide a common framework for the general timing analysis of such circuits. The inclusion of additional constraints into the problem formulation in order to meet the timing requirements imposed by specific applicationenvironments is discussed

    Advanced Timing and Synchronization Methodologies for Digital VLSI Integrated Circuits

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    This dissertation addresses timing and synchronization methodologies that are critical to the design, analysis and optimization of high-performance, integrated digital VLSI systems. As process sizes shrink and design complexities increase, achieving timing closure for digital VLSI circuits becomes a significant bottleneck in the integrated circuit design flow. Circuit designers are motivated to investigate and employ alternative methods to satisfy the timing and physical design performance targets. Such novel methods for the timing and synchronization of complex circuitry are developed in this dissertation and analyzed for performance and applicability.Mainstream integrated circuit design flow is normally tuned for zero clock skew, edge-triggered circuit design. Non-zero clock skew or multi-phase clock synchronization is seldom used because the lack of design automation tools increases the length and cost of the design cycle. For similar reasons, level-sensitive registers have not become an industry standard despite their superior size, speed and power consumption characteristics compared to conventional edge-triggered flip-flops.In this dissertation, novel design and analysis techniques that fully automate the design and analysis of non-zero clock skew circuits are presented. Clock skew scheduling of both edge-triggered and level-sensitive circuits are investigated in order to exploit maximum circuit performances. The effects of multi-phase clocking on non-zero clock skew, level-sensitive circuits are investigated leading to advanced synchronization methodologies. Improvements in the scalability of the computational timing analysis process with clock skew scheduling are explored through partitioning and parallelization.The integration of the proposed design and analysis methods to the physical design flow of integrated circuits synchronized with a next-generation clocking technology-resonant rotary clocking technology-is also presented. Based on the design and analysis methods presented in this dissertation, a computer-aided design tool for the design of rotary clock synchronized integrated circuits is developed

    둜직 및 피지컬 ν•©μ„±μ—μ„œμ˜ 타이밍 뢄석과 μ΅œμ ν™”

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    ν•™μœ„λ…Όλ¬Έ (박사) -- μ„œμšΈλŒ€ν•™κ΅ λŒ€ν•™μ› : κ³΅κ³ΌλŒ€ν•™ 전기·정보곡학뢀, 2020. 8. κΉ€νƒœν™˜.Timing analysis is one of the necessary steps in the development of a semiconductor circuit. In addition, it is increasingly important in the advanced process technologies due to various factors, including the increase of process–voltage–temperature variation. This dissertation addresses three problems related to timing analysis and optimization in logic and physical synthesis. Firstly, most static timing analysis today are based on conventional fixed flip-flop timing models, in which every flip-flop is assumed to have a fixed clock-to-Q delay. However, setup and hold skews affect the clock-to-Q delay in reality. In this dissertation, I propose a mathematical formulation to solve the problem and apply it to the clock skew scheduling problems as well as to the analysis of a given circuit, with a scalable speedup technique. Secondly, near-threshold computing is one of the promising concepts for energy-efficient operation of VLSI systems, but wide performance variation and nonlinearity to process variations block the proliferation. To cope with this, I propose a holistic hardware performance monitoring methodology for accurate timing prediction in a near-threshold voltage regime and advanced process technology. Lastly, an asynchronous circuit is one of the alternatives to the conventional synchronous style, and asynchronous pipeline circuit especially attractive because of its small design effort. This dissertation addresses the synthesis problem of lightening two-phase bundled-data asynchronous pipeline controllers, in which delay buffers are essential for guaranteeing the correct handshaking operation but incurs considerable area increase.타이밍 뢄석은 λ°˜λ„μ²΄ 회둜 개발 ν•„μˆ˜ κ³Όμ • 쀑 ν•˜λ‚˜λ‘œ, μ΅œμ‹  κ³΅μ •μΌμˆ˜λ‘ 곡정-μ „μ••-μ˜¨λ„ 변이 증가λ₯Ό ν¬ν•¨ν•œ λ‹€μ–‘ν•œ μš”μΈμœΌλ‘œ ν•˜μ—¬κΈˆ κ·Έ μ€‘μš”μ„±μ΄ 컀지고 μžˆλ‹€. λ³Έ λ…Όλ¬Έμ—μ„œλŠ” 둜직 및 피지컬 ν•©μ„±κ³Ό κ΄€λ ¨ν•˜μ—¬ μ„Έ 가지 타이밍 뢄석 및 μ΅œμ ν™” λ¬Έμ œμ— λŒ€ν•΄ 닀룬닀. 첫째둜, μ˜€λŠ˜λ‚  λŒ€λΆ€λΆ„μ˜ 정적 타이밍 뢄석은 λͺ¨λ“  ν”Œλ¦½-ν”Œλ‘­μ˜ 클럭-좜λ ₯ λ”œλ ˆμ΄κ°€ κ³ μ •λœ κ°’μ΄λΌλŠ” 가정을 λ°”νƒ•μœΌλ‘œ μ΄λ£¨μ–΄μ‘Œλ‹€. ν•˜μ§€λ§Œ μ‹€μ œ 클럭-좜λ ₯ λ”œλ ˆμ΄λŠ” ν•΄λ‹Ή ν”Œλ¦½-ν”Œλ‘­μ˜ μ…‹μ—… 및 ν™€λ“œ μŠ€νμ— 영ν–₯을 λ°›λŠ”λ‹€. λ³Έ λ…Όλ¬Έμ—μ„œλŠ” μ΄λŸ¬ν•œ νŠΉμ„±μ„ μˆ˜ν•™μ μœΌλ‘œ μ •λ¦¬ν•˜μ˜€μœΌλ©°, 이λ₯Ό ν™•μž₯ κ°€λŠ₯ν•œ 속도 ν–₯상 기법과 λ”λΆˆμ–΄ 주어진 회둜의 타이밍 뢄석 및 클럭 슀큐 μŠ€μΌ€μ₯΄λ§ λ¬Έμ œμ— μ μš©ν•˜μ˜€λ‹€. λ‘˜μ§Έλ‘œ, μœ μ‚¬ λ¬Έν„± 연산은 μ΄ˆκ³ μ§‘μ  회둜 λ™μž‘μ˜ μ—λ„ˆμ§€ νš¨μœ¨μ„ λŒμ–΄ 올릴 수 μžˆλ‹€λŠ” μ μ—μ„œ κ°κ΄‘λ°›μ§€λ§Œ, 큰 폭의 μ„±λŠ₯ 변이 및 λΉ„μ„ ν˜•μ„± λ•Œλ¬Έμ— 널리 ν™œμš©λ˜κ³  μžˆμ§€ μ•Šλ‹€. 이λ₯Ό ν•΄κ²°ν•˜κΈ° μœ„ν•΄ μœ μ‚¬ λ¬Έν„± μ „μ•• μ˜μ—­ 및 μ΅œμ‹  곡정 λ…Έλ“œμ—μ„œ 보닀 μ •ν™•ν•œ 타이밍 μ˜ˆμΈ‘μ„ μœ„ν•œ ν•˜λ“œμ›¨μ–΄ μ„±λŠ₯ λͺ¨λ‹ˆν„°λ§ 방법둠 μ „λ°˜μ„ μ œμ•ˆν•˜μ˜€λ‹€. λ§ˆμ§€λ§‰μœΌλ‘œ, 비동기 νšŒλ‘œλŠ” κΈ°μ‘΄ 동기 회둜의 λŒ€μ•ˆ 쀑 ν•˜λ‚˜λ‘œ, κ·Έ μ€‘μ—μ„œλ„ 비동기 νŒŒμ΄ν”„λΌμΈ νšŒλ‘œλŠ” 비ꡐ적 적은 섀계 λ…Έλ ₯λ§ŒμœΌλ‘œλ„ κ΅¬ν˜„ κ°€λŠ₯ν•˜λ‹€λŠ” μž₯점이 μžˆλ‹€. λ³Έ λ…Όλ¬Έμ—μ„œλŠ” 2μœ„μƒ 묢음 데이터 ν”„λ‘œν† μ½œ 기반 비동기 νŒŒμ΄ν”„λΌμΈ 컨트둀러 μƒμ—μ„œ, μ •ν™•ν•œ ν•Έλ“œμ…°μ΄ν‚Ή 톡신을 μœ„ν•΄ μ‚½μž…λœ λ”œλ ˆμ΄ 버퍼에 μ˜ν•œ 면적 증가λ₯Ό μ™„ν™”ν•  수 μžˆλŠ” ν•©μ„± 기법을 μ œμ‹œν•˜μ˜€λ‹€.1 INTRODUCTION 1 1.1 Flexible Flip-Flop Timing Model 1 1.2 Hardware Performance Monitoring Methodology 4 1.3 Asynchronous Pipeline Controller 10 1.4 Contributions of this Dissertation 15 2 ANALYSIS AND OPTIMIZATION CONSIDERING FLEXIBLE FLIP-FLOP TIMING MODEL 17 2.1 Preliminaries 17 2.1.1 Terminologies 17 2.1.2 Timing Analysis 20 2.1.3 Clock-to-Q Delay Surface Modeling 21 2.2 Clock-to-Q Delay Interval Analysis 22 2.2.1 Derivation 23 2.2.2 Additional Constraints 26 2.2.3 Analysis: Finding Minimum Clock Period 28 2.2.4 Optimization: Clock Skew Scheduling 30 2.2.5 Scalable Speedup Technique 33 2.3 Experimental Results 37 2.3.1 Application to Minimum Clock Period Finding 37 2.3.2 Application to Clock Skew Scheduling 39 2.3.3 Efficacy of Scalable Speedup Technique 43 2.4 Summary 44 3 HARDWARE PERFORMANCE MONITORING METHODOLOGY AT NTC AND ADVANCED TECHNOLOGY NODE 45 3.1 Overall Flow of Proposed HPM Methodology 45 3.2 Prerequisites to HPM Methodology 47 3.2.1 BEOL Process Variation Modeling 47 3.2.2 Surrogate Model Preparation 49 3.3 HPM Methodology: Design Phase 52 3.3.1 HPM2PV Model Construction 52 3.3.2 Optimization of Monitoring Circuits Configuration 54 3.3.3 PV2CPT Model Construction 58 3.4 HPM Methodology: Post-Silicon Phase 60 3.4.1 Transfer Learning in Silicon Characterization Step 60 3.4.2 Procedures in Volume Production Phase 61 3.5 Experimental Results 62 3.5.1 Experimental Setup 62 3.5.2 Exploration of Monitoring Circuits Configuration 64 3.5.3 Effectiveness of Monitoring Circuits Optimization 66 3.5.4 Considering BEOL PVs and Uncertainty Learning 68 3.5.5 Comparison among Different Prediction Flows 69 3.5.6 Effectiveness of Prediction Model Calibration 71 3.6 Summary 73 4 LIGHTENING ASYNCHRONOUS PIPELINE CONTROLLER 75 4.1 Preliminaries and State-of-the-Art Work 75 4.1.1 Bundled-data vs. Dual-rail Asynchronous Circuits 75 4.1.2 Two-phase vs. Four-phase Bundled-data Protocol 76 4.1.3 Conventional State-of-the-Art Pipeline Controller Template 77 4.2 Delay Path Sharing for Lightening Pipeline Controller Template 78 4.2.1 Synthesizing Sharable Delay Paths 78 4.2.2 Validating Logical Correctness for Sharable Delay Paths 80 4.2.3 Reformulating Timing Constraints of Controller Template 81 4.2.4 Minimally Allocating Delay Buffers 87 4.3 In-depth Pipeline Controller Template Synthesis with Delay Path Reusing 88 4.3.1 Synthesizing Delay Path Units 88 4.3.2 Validating Logical Correctness of Delay Path Units 89 4.3.3 Updating Timing Constraints for Delay Path Units 91 4.3.4 In-depth Synthesis Flow Utilizing Delay Path Units 95 4.4 Experimental Results 99 4.4.1 Environment Setup 99 4.4.2 Piecewise Linear Modeling of Delay Path Unit Area 99 4.4.3 Comparison of Power, Performance, and Area 102 4.5 Summary 107 5 CONCLUSION 109 5.1 Chapter 2 109 5.2 Chapter 3 110 5.3 Chapter 4 110 Abstract (In Korean) 127Docto

    EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers

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    At nanometer manufacturing technology nodes, process variations significantly affect circuit performance. To combat them, post- silicon clock tuning buffers can be deployed to balance timing bud- gets of critical paths for each individual chip after manufacturing. The challenge of this method is that path delays should be mea- sured for each chip to configure the tuning buffers properly. Current methods for this delay measurement rely on path-wise frequency stepping. This strategy, however, requires too much time from ex- pensive testers. In this paper, we propose an efficient delay test framework (EffiTest) to solve the post-silicon testing problem by aligning path delays using the already-existing tuning buffers in the circuit. In addition, we only test representative paths and the delays of other paths are estimated by statistical delay prediction. Exper- imental results demonstrate that the proposed method can reduce the number of frequency stepping iterations by more than 94% with only a slight yield loss.Comment: ACM/IEEE Design Automation Conference (DAC), June 201

    Exploiting Adaptive Techniques to Improve Processor Energy Efficiency

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    Rapid device-miniaturization keeps on inducing challenges in building energy efficient microprocessors. As the size of the transistors continuously decreasing, more uncertainties emerge in their operations. On the other hand, integrating more and more transistors on a single chip accentuates the need to lower its supply-voltage. This dissertation investigates one of the primary device uncertainties - timing error, in microprocessor performance bottleneck in NTC era. Then it proposes various innovative techniques to exploit these opportunities to maintain processor energy efficiency, in the context of emerging challenges. Evaluated with the cross-layer methodology, the proposed approaches achieve substantial improvements in processor energy efficiency, compared to other start-of-art techniques

    Statistical static timing analysis of nonzero clock skew circuit

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    As microprocessor and ASIC manufacturers continue to push the limits of transistor sizing into the sub-100nm regime, variations in the manufacturing process lead to increased uncertainty about the exact geometry and performance of the resulting devices. Traditional corner-based Static Timing Analysis (STA) assumes worst-case values for process parameters such as transistor channel length and threshold voltage when verifying integrated circuit timing performance. This has become unrea-sonably pessimistic and causes over-design that degrades full-chip performance, wastes engineering effort, and erodes profits while providing negligible yield improvement. Recently, Statistical Static Timing Analysis (SSTA) methods, which model process variations statistically as probability distribution functions (PDFs) rather than deterministically, have emerged to more accurately portray integrated circuit performance. This analysis has been thoroughly performed on traditional zero clock skew circuits where the synchronizing clock signal is assumed to arrive in phase with respect to each register. However, designers will often schedule the clock skew to different registers in order to decrease the minimum clock period of the entire circuit. Clock skew scheduling (CSS) imparts very different timing constraints that are based, in part, on the topology of the circuit. In this thesis, SSTA is applied to nonzero clock skew circuits in order to determine the accuracy improvement relative to their zero skew counterparts, and also to assess how the results of skew scheduling might be impacted with more accurate statistical modeling. For 99.7% timing yield (3 variation), SSTA is observed to improve the accuracy, and therefore increase the timing margin, of nonzero clock skew circuits by up to 2.5x, and on average by 1.3x, the amount seen by zero skew circuits.M.S., Computer Engineering -- Drexel University, 200

    Yield-Driven, False-Path-Aware Clock Skew Scheduling

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