Integrating Abstract Caches with Symbolic Pipeline Analysis

Static worst-case execution time analysis of real-time tasks is based on abstract models that capture the timing behavior of the processor on which the tasks run. For complex processors, task-level execution time bounds are obtained by a state space exploration which involves the abstract model and the program. Partial state space exploration is not sound. Symbolic methods using binary decision diagrams (BDDs) allow for a full state space exploration of the pipeline, thereby maintaining soundness. Caches are too large to admit an efficient BDD representation. On the other hand, invariants of the cache state can be computed efficiently using abstract interpretation. How to integrate abstract caches with symbolic-state pipeline analysis is an open question. We propose a semi-symbolic domain to solve this problem. Statistical data from industrial-level software and WCET tools indicate that this new domain will enable an efficient analysis

EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers

At nanometer manufacturing technology nodes, process variations significantly affect circuit performance. To combat them, post- silicon clock tuning buffers can be deployed to balance timing bud- gets of critical paths for each individual chip after manufacturing. The challenge of this method is that path delays should be mea- sured for each chip to configure the tuning buffers properly. Current methods for this delay measurement rely on path-wise frequency stepping. This strategy, however, requires too much time from ex- pensive testers. In this paper, we propose an efficient delay test framework (EffiTest) to solve the post-silicon testing problem by aligning path delays using the already-existing tuning buffers in the circuit. In addition, we only test representative paths and the delays of other paths are estimated by statistical delay prediction. Exper- imental results demonstrate that the proposed method can reduce the number of frequency stepping iterations by more than 94% with only a slight yield loss.Comment: ACM/IEEE Design Automation Conference (DAC), June 201

Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability

At submicron manufacturing technology nodes process variations affect circuit performance significantly. This trend leads to a large timing margin and thus overdesign to maintain yield. To combat this pessimism, post-silicon clock tuning buffers can be inserted into circuits to balance timing budgets of critical paths with their neighbors. After manufacturing, these clock buffers can be configured for each chip individually so that chips with timing failures may be rescued to improve yield. In this paper, we propose a sampling-based method to determine the proper locations of these buffers. The goal of this buffer insertion is to reduce the number of buffers and their ranges, while still maintaining a good yield improvement. Experimental results demonstrate that our algorithm can achieve a significant yield improvement (up to 35%) with only a small number of buffers.Comment: Design, Automation and Test in Europe (DATE), 201

On Timing Model Extraction and Hierarchical Statistical Timing Analysis

In this paper, we investigate the challenges to apply Statistical Static Timing Analysis (SSTA) in hierarchical design flow, where modules supplied by IP vendors are used to hide design details for IP protection and to reduce the complexity of design and verification. For the three basic circuit types, combinational, flip-flop-based and latch-controlled, we propose methods to extract timing models which contain interfacing as well as compressed internal constraints. Using these compact timing models the runtime of full-chip timing analysis can be reduced, while circuit details from IP vendors are not exposed. We also propose a method to reconstruct the correlation between modules during full-chip timing analysis. This correlation can not be incorporated into timing models because it depends on the layout of the corresponding modules in the chip. In addition, we investigate how to apply the extracted timing models with the reconstructed correlation to evaluate the performance of the complete design. Experiments demonstrate that using the extracted timing models and reconstructed correlation full-chip timing analysis can be several times faster than applying the flattened circuit directly, while the accuracy of statistical timing analysis is still well maintained

Gravitational wave astronomy of single sources with a pulsar timing array

Abbreviated: We investigate the potential of detecting the gravitational wave from individual binary black hole systems using pulsar timing arrays (PTAs) and calculate the accuracy for determining the GW properties. This is done in a consistent analysis, which at the same time accounts for the measurement of the pulsar distances via the timing parallax. We find that, at low redshift, a PTA is able to detect the nano-Hertz GW from super massive black hole binary systems with masses of \sim10^8 - 10^{10}\,M_{\sun} less than $\sim10^5$\,years before the final merger, and those with less than $\sim10^3 - 10^4$ years before merger may allow us to detect the evolution of binaries. We derive an analytical expression to describe the accuracy of a pulsar distance measurement via timing parallax. We consider five years of bi-weekly observations at a precision of 15\,ns for close-by ($\sim 0.5 - 1$\,kpc) pulsars. Timing twenty pulsars would allow us to detect a GW source with an amplitude larger than $5\times 10^{-17}$. We calculate the corresponding GW and binary orbital parameters and their measurement precision. The accuracy of measuring the binary orbital inclination angle, the sky position, and the GW frequency are calculated as functions of the GW amplitude. We note that the "pulsar term", which is commonly regarded as noise, is essential for obtaining an accurate measurement for the GW source location. We also show that utilizing the information encoded in the GW signal passing the Earth also increases the accuracy of pulsar distance measurements. If the gravitational wave is strong enough, one can achieve sub-parsec distance measurements for nearby pulsars with distance less than $\sim 0.5 - 1$\,kpc.Comment: 16 pages, 5 figure,, accepted by MNRA