Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm

3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability.Peer ReviewedPostprint (author's final draft

RRAM variability and its mitigation schemes

Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures, such as process variation due to their nano-scale structure have gained considerable importance for acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit system level. In this paper we have analyzed the RRAM variability phenomenon, its impact and variation tolerant techniques at the circuit level. Finally a variation-monitoring circuit is presented that discerns the reliable memory cells affected by process variability.Peer ReviewedPostprint (author's final draft

Yield improvement using configurable analogue transistors (CATs)

Continued process scaling has led to significant yield and reliability challenges for today’s designers. Analogue circuits are particularly susceptible to poor variation, driving the need for new yield resilient techniques in this area. This paper describes a new configurable analogue transistor structure and supporting methodology that facilitates variation compensation at the post-manufacture stage. The approach has demonstrated significant yield improvements and can be applied to any analogue circui

Fast, non-monte-carlo estimation of transient performance variation due to device mismatch

This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency. The proposed method models DC random offsets as equivalent AC pseudo-noises and leverages the fast, linear periodically time-varying (LPTV) noise analysis available from RF circuit simulators. Therefore, the method can be considered as an extension to DC match analysis and offers a large speed-up compared to the traditional Monte-Carlo analysis. Although the assumed linear perturbation model is valid only for small variations, it enables easy ways to estimate correlations among variations and identify the most sensitive design parameters to mismatch, all at no additional simulation cost. Three benchmarks measuring the variations in the input offset voltage of a clocked comparator, the delay of a logic path, and the frequency of an oscillator demonstrate the speed improvement of about 100-1000x compared to a 1000-point Monte-Carlo method

Comparison between bulk and FDSOI POM flash cell: a multiscale simulation study

In this brief, we present a multiscale simulation study of a fully depleted silicon-on-insulator (FDSOI) nonvolatile memory cell based on polyoxometalates (POMs) inorganic molecular clusters used as a storage media embedded in the gate dielectric of flash cells. In particular, we focus our discussion on the threshold voltage variability introduced by random discrete dopants (random dopant fluctuation) and by fluctuations in the distribution of the POM molecules in the storage media (POM fluctuation). To highlight the advantages of the FDSOI POM flash cell, we provide a comparison with an equivalent cell based on conventional (BULK) transistors. The presented simulation framework and methodology is transferrable to flash cells based on alternative molecules used as a storage media

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis

Impact of parameter variations on circuits and microarchitecture

Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace with performance scaling and to keep power consumption within reasonable limits. This article presents an overview of the main sources of variability and surveys variation-tolerant circuit and microarchitectural approaches.Peer ReviewedPostprint (published version

Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-diffusion with nonequilibrium Green functions simulations, we show that quantum effects in the charge distribution and transport can reduce or amplify the impact of discrete traps in simulation of reliability resilience of scaled FinFETs

Reliability analysis and micromechanics: A coupled approach for composite failure prediction

This work aims at associating two classical approaches for the design of composite materials: first, reliability methods that allow to account for the various uncertainties involved in the composite materials behaviour and lead to a rational estimation of their reliability level; on the other hand, micromechanics that derive macroscopic constitutive laws from micromechanical features. Such approach relies on the introduction of variabilities defined at the microscale and on the investigation of their consequences on the material macroscopic response through an homogenization scheme. Precisely, we propose here a systematic treatment of variability which involves a strong link between micro- and macroscales and provides a more exhaustive analysis of the influence of uncertainties. The paper intends to explain the main steps of such coupling and demonstrate its interests for material engineering, especially for constitutive modelling and composite materials optimization. An application case is developed throughout on the failure of unidirectional carbon fibre-reinforced composites with a comparative analysis between experimental data and simulation results