Transport models and advanced numerical simulation of silicon-germanium heterojunction bipolar transistors

Applications in the emerging high-frequency markets for millimeter wave applications more and more use SiGe components for cost reasons. To support the technology effort, a reliable TCAD platform is required. The main issue in the simulation of scaled devices is related to the limitations of the physical models used to describe charge carrier transport. Inherent approximations in the HD formalism are discussed over different technology nodes, providing for the first time a complete survey of HD models capability and restrictions with scaling for simulation of SiGe HBTs. Moreover, a complete set of models for transport parameters of SiGe HBTs is reported, including low-field mobility, energy relaxation time, saturation velocity, high-field mobility and effective density of state. Implementation in a commercial device simulator is drawn and findings are compared with simulation results obtained using a standard set of models and with trustworthy results (i.e. MC and SHE simulation results and experimental data), validating proposed models and clarifying their reliability and accuracy over different technologies. Finally, electrical breakdown phenomena in SiGe HBTs are analyzed: a novel complete model for multiplication factor is reported and validated by experimental results; new M model provides an exhaustive accuracy over a wide range of collector voltages

34th Midwest Symposium on Circuits and Systems-Final Program

Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi

Design And Characterization Of Noveldevices For New Generation Of Electrostaticdischarge (esd) Protection Structures

The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications\u27 performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Improving the Readout of Semiconducting Qubits

Semiconducting qubits are a promising platform for quantum computers. In particular, silicon spin qubits have made a number of advancements recently including long coherence times, high-fidelity single-qubit gates, two-qubit gates, and high-fidelity readout. However, all operations likely require improvement in fidelity and speed, if possible, to realize a quantum computer. Readout fidelity and speed, in general, are limited by circuit challenges centered on extracting low signal from a device in a dilution refrigerator connected to room temperature amplifiers by long coaxial cables with relatively high capacitance. Readout fidelity specifically is limited by the time it takes to reliably distinguish qubit states relative to the characteristic decay time of the excited state, T1. This dissertation explores the use of heterojunction bipolar transistor (HBT) circuits to amplify the readout signal of silicon spin qubits at cryogenic temperatures. The cryogenic amplification approach has numerous advantages including low implementation overhead, low power relative to the available cooling power, and high signal gain at the mixing chamber stage leading to around a factor of ten speedup in readout time for a similar signal-to-noise ratio. The faster readout time generally increases fidelity, since it is much faster than the T1 time. Two HBT amplification circuits have been designed and characterized. One design is a low-power, base-current biased configuration with non-linear gain (CB-HBT), and the second is a linear-gain, AC-coupled configuration (AC-HBT). They can operate at powers of 1 and 10 μW, respectfully, and not significantly heat electrons. The noise spectral density referred to the input for both circuits is around 15 to 30 fA/√Hz, which is low compared to previous cases such as the dual-stage, AC-coupled HEMT circuit at ~ 70 fA/√Hz. Both circuits achieve charge sensitivity between 300 and 400 μe/√Hz, which approaches the best alternatives (e.g., RF-SET at ~ 140 μe/√Hz) but with much less implementation overhead. For the single-shot latched charge readout performed, both circuits achieve high-fidelity readout in times \u3c 10 μs with bit error rates \u3c 10-3, which is a great improvement over previous work at \u3e 70 μs. The readout speed-up in principle also reduces the production of errors due to excited state relaxation by a factor of ~ 10. All of these results are possible with relatively simple, low-power transistor circuits which can be mounted close to the qubit device at the mixing chamber stage of the dilution refrigerator

Technology Advances for Radio Astronomy

The field of radio astronomy continues to provide fundamental contributions to the understanding of the evolution, and inner workings of, our universe. It has done so from its humble beginnings, where single antennas and receivers were used for observation, to today's focal plane arrays and interferometers. The number of receiving elements (pixels) in these instruments is quickly growing, currently approaching one hundred. For the instruments of tomorrow, the number of receiving elements will be in the thousands. Such instruments will enable researchers to peer deeper into the fabric of our universe and do so at faster survey speeds. They will provide enormous capability, both for unraveling today's mysteries as well as for the discovery of new phenomena. Among other challenges, producing the large numbers of low-noise amplifiers required for these instruments will be no easy task. The work described in this thesis advances the state of the art in three critical areas, technological advancements necessary for the future design and manufacturing of thousands of low-noise amplifiers. These areas being: the automated, cryogenic, probing of \diameter100 mm indium phosphide wafers; a system for measuring the noise parameters of devices at cryogenic temperatures; and the development of low-noise, silicon germanium amplifiers for terahertz mixer receivers. The four chapters that comprise the body of this work detail the background, design, assembly, and testing involved in these contributions. Also included is a brief survey of noise parameters, the knowledge of which is fundamental to the design of low-noise amplifiers and the optimization of the system noise temperature for large, dense, interferometers.</p

Silicon Integrated Arrays: From Microwave to IR

Integrated chips have enabled realization and mass production of complex systems in a small form factor. Through process miniaturization many novel applications in silicon photonics and electronic systems have been enabled. In this thesis I have provided several examples of innovations that are only enabled by integration. I have also demonstrated how electronics and photonics circuits can complement each other to achieve a system with superior performance.</p

Efficient wireless coverage of in-building environments with low electromagnetic impact

The city of tomorrow is a major integrating stake, which crosses a set of major broad spectrum domains. One of these areas is the instrumentation of this city and the ubiquity of the exchange of data, which will give the pulse of this city (sensors) and its breathing in a hyper-connected world within indoor and outdoor dense areas (data exchange, 5G and 6G). Within this context, the proposed doctorate project has the objective to realize cost- and energy- effective, short-range communication systems for the capillary wireless coverage of in-door environments with low electromagnetic impact and for highly dense outdoor networks. The result will be reached through the combined use of: 1) Radio over Fiber (RoF) Technology, to bring the Radio Frequency (RF) signal to the different areas to be covered. 2) Beamforming antennas to send in real time the RF power just in the direction(s) where it is really necessary