Attitude orientation of spin-stabilized space vehicles Patent

Attitude orientation control of spin stabilized final stage space vehicles, using horizon scanner

Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations

Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations

タンセン ニュウリョク NAND カイロ ト NOR カイロ ノ カンヤクケイ ノ ドウジ ロンリ セッケイ

Simultaneous logic design of NAND circuit and NOR circuit with monorailed input are discussed in this paper. Complete logical sum and complete logical product, which are induced by dual Karnaugh Mapping, are utilized as the designing methode. Discussion, as for 3-staged NAND (or NOR) circuits, are of minimum form, input output level adjusting, and stability of switching. Satisfactory performance are obtained comparing with computer programmed method utilizing Petric funcion

Program to design, fabricate, test, and deliver a thermal control-mixing control device for the George C. Marshall Space Flight Center

The development and testing of a temperature sensor and pulse duration modulation (PDM) diverter valve for a thermal control-mixing control device are described. The temperature sensor selected for use uses a fluidic pin amplifier in conjunction with an expansion device. This device can sense changes of less than 0.25 F with greater than 15:1 signal to noise ratio when operating with a typical Freon pump supplied pressure. The pressure sensitivity of the sensor is approximately 0.0019 F/kPa. The valve which was selected was tested and performed with 100% flow diversion. In addition, the valve operates with a flow efficiency of at least 95%, with the possibility of attaining 100% if the vent flow of the PDM can be channeled through the last stage of the diverter valve. A temperature sensor which utilized an orifice bridge circuit and proportional-vortex combination mixing valve were also evaluated, but the concepts were rejected due to various problems

Staged opening switch

" A staged switch for conducting a large electrical current for an indefinite time period and then rapidly switching the current into a load circuit. The switch comprises a first stage which can conduct a large electrical current for an indefinite time period without damage to the stage and a second stage which is a fast-opening element. The first stage includes primary and secondary contacts wherein the primary contacts conduct a charging current and the secondary contacts divert the current into the fast-opening second stage. The secondary contacts ""make"" before the primary contacts ""break"", reducing the damage to the contacts which might otherwise be experienced. The second stage is a low-inductance element which reduces the level of energy absorbed by the first-stage contacts, minimizing damage to the contacts. The second-stage element may be constructed in a cartridge and may be loaded into the switch using an autoloader device. "Board of Regents, University of Texas Syste

Analysis of Multi Resonant Switched Capacitive Converter with Imbedded PCB Elements

The data center industry is headed towards a lower point of load voltages with increased load demands contributing to higher I2R losses in power busses. Raising the bus voltage from 12V to 48V is a popular area investigated today for reducing power delivery losses. Switched capacitive converters (SCCs) are a popular topology used for this purpose. However, SCCs suffer from low tolerance for operating conditions and are unregulated. The proposed multi resonant switched capacitor buck converter (MRSCBC) can resolve these challenges while also providing output regulation. Switch mode power supplies exhibit high electromagnetic noise and with an increased number of switches in an MRSCBC, controlling EMI noise and compatibility is essential. This thesis will focus on the use of PCB design and software simulations to optimize electromagnetic interference (EMI) and parasitic elements in the traces to improve the robustness of an MRSCBC

Arcing High Impedance Fault Detection Using Real Coded Genetic Algorithm

Safety and reliability are two of the most important aspects of electric power supply systems. Sensitivity and robustness to detect and isolate faults can influence the safety and reliability of such systems. Overcurrent relays are generally used to protect the high voltage feeders in distribution systems. Downed conductors, tree branches touching conductors, and failing insulators often cause high-impedance faults in overhead distribution systems. The levels of currents of these faults are often much smaller than detection thresholds of traditional ground fault detection devices, thus reliable detection of these high impedance faults is a real challenge. With modern signal processing techniques, special hardware and software can be used to significantly improve the reliability of detection of certain types of faults. This paper presents a new method for detecting High Impedance Faults (HIF) in distribution systems using real coded genetic algorithm (RCGA) to analyse the harmonics and phase angles of the fault current signals. The method is used to discriminate HIFs by identifying specific events that happen when a HIF occurs