Generating general-purpose cutting planes for mixed-integer programs

Franz WesselmannPaderborn, Univ., Diss., 201

Distances to lattice points in rational polyhedra

Let a ∈ Z n >0 , n ≥ 2 , gcd(a) := gcd(a1 , . . . , an ) = 1, b ∈ Z≥0 and denote by k · k∞ the ℓ∞-norm. Consider the knapsack polytope P(a, b) = { x ∈ R n ≥0 : a T x = b and assume that P(a, b) ∩ Z n 6= ; holds. The main result of this thesis states that for any vertex x ∗ of the knapsack polytope P(a, b) there exists a feasible integer point z ∗ ∈ P(a, b) such that, denoting by s the size of the support of z ∗ , i.e. the number of nonzero components in z ∗ and upon assuming s > 0 , the inequality kx ∗ − z ∗ k∞ 2 s−1 s < kak∞ holds. This inequality may be viewed as a transference result which allows strengthening the best known distance (proximity) bounds if integer points are not sparse and, vice versa, strengthening the best known sparsity bounds if feasible integer points are sufficiently far from a vertex of the knapsack polytope. In particular, this bound provides an exponential in s improvement on the previously best known distance bounds in the knapsack scenario. Further, when considering general integer linear programs, we show that a resembling inequality holds for vertices of Gomory’s corner polyhedra [49, 96]. In addition, we provide several refinements of the known distance and support bounds under additional assumption

The Hirsch Conjecture for the fractional stable set polytope

The edge formulation of the stable set problem is defined by two-variable constraints, one for each edge of a graph $$G$$ G , expressing the simple condition that two adjacent nodes cannot belong to a stable set. We study the fractional stable set polytope, i.e. the polytope defined by the linear relaxation of the edge formulation. Even if this polytope is a weak approximation of the stable set polytope, its simple geometrical structure provides deep theoretical insight as well as interesting algorithmic opportunities. Exploiting a graphic characterization of the bases, we first redefine pivots in terms of simple graphic operations, that turn a given basis into an adjacent one. These results lead us to prove that the combinatorial diameter of the fractional stable set polytope is at most the number of nodes of the given graph. As a corollary, the Hirsch bound holds for this class of polytopes

VLSI Routing for Advanced Technology

Routing is a major step in VLSI design, the design process of complex integrated circuits (commonly known as chips). The basic task in routing is to connect predetermined locations on a chip (pins) with wires which serve as electrical connections. One main challenge in routing for advanced chip technology is the increasing complexity of design rules which reflect manufacturing requirements. In this thesis we investigate various aspects of this challenge. First, we consider polygon decomposition problems in the context of VLSI design rules. We introduce different width notions for polygons which are important for width-dependent design rules in VLSI routing, and we present efficient algorithms for computing width-preserving decompositions of rectilinear polygons into rectangles. Such decompositions are used in routing to allow for fast design rule checking. A main contribution of this thesis is an O(n) time algorithm for computing a decomposition of a simple rectilinear polygon with n vertices into O(n) rectangles, preseverving two-dimensional width. Here the two-dimensional width at a point of the polygon is defined as the edge length of a largest square that contains the point and is contained in the polygon. In order to obtain these results we establish a connection between such decompositions and Voronoi diagrams. Furthermore, we consider implications of multiple patterning and other advanced design rules for VLSI routing. The main contribution in this context is the detailed description of a routing approach which is able to manage such advanced design rules. As a main algorithmic concept we use multi-label shortest paths where certain path properties (which model design rules) can be enforced by defining labels assigned to path vertices and allowing only certain label transitions. The described approach has been implemented in BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics, University of Bonn, in cooperation with IBM. We present experimental results confirming that a flow combining BonnRoute and an external cleanup step produces far superior results compared to an industry standard router. In particular, our proposed flow runs more than twice as fast, reduces the via count by more than 20%, the wiring length by more than 10%, and the number of remaining design rule errors by more than 60%. These results obtained by applying our multiple patterning approach to real-world chip instances provided by IBM are another main contribution of this thesis. We note that IBM uses our proposed combined BonnRoute flow as the default tool for signal routing

LIPIcs, Volume 258, SoCG 2023, Complete Volume

LIPIcs, Volume 258, SoCG 2023, Complete Volum