SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips

This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of nominal and non-ideal operation of CNN analogue circuitry at the behavioural level; (b) performing realistic simulations of the transient evolution of physical CNNs including deviations due to second-order effects of the hardware; and, (c) evaluating sensitivity figures, and realize noise and Monte Carlo simulations in the time domain. These capabilities portray SIRENA as better suited for CNN chip development than algorithmic simulation packages (such as OpenSimulator, Sesame) or conventional neural networks simulators (RCS, GENESIS, SFINX), which are not oriented to the evaluation of hardware non-idealities. As compared to conventional electrical simulators (such as HSPICE or ELDO-FAS), SIRENA provides easier modelling of the hardware parasitics, a significant reduction in computation time, and similar accuracy levels. Consequently, iteration during the design procedure becomes possible, supporting decision making regarding design strategies and dimensioning. SIRENA has been developed using object-oriented programming techniques in C, and currently runs under the UNIX operating system and X-Windows framework. It employs a dedicated high-level hardware description language: DECEL, fitted to the description of non-idealities arising in CNN hardware. This language has been developed aiming generality, in the sense of making no restrictions on the network models that can be implemented. SIRENA is highly modular and composed of independent tools. This simplifies future expansions and improvements.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploitation of current mirror properties for the efficient implementation of both linear and nonlinear analog operators. These cells are simpler and easier to design than those found in previously reported CT and DT-CNN devices. Basic design issues are covered, together with discussions on the influence of nonidealities and advanced circuit design issues as well as design for manufacturability considerations associated with statistical analysis. Three prototypes have been designed for l.6-pm n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. Experimental results are given illustrating performance of these prototypes

Neuro-memristive Circuits for Edge Computing: A review

The volume, veracity, variability, and velocity of data produced from the ever-increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing

Silicon Atomic Quantum Dots Enable Beyond-CMOS Electronics

We review our recent efforts in building atom-scale quantum-dot cellular automata circuits on a silicon surface. Our building block consists of silicon dangling bond on a H-Si(001) surface, which has been shown to act as a quantum dot. First the fabrication, experimental imaging, and charging character of the dangling bond are discussed. We then show how precise assemblies of such dots can be created to form artificial molecules. Such complex structures can be used as systems with custom optical properties, circuit elements for quantum-dot cellular automata, and quantum computing. Considerations on macro-to-atom connections are discussed.Comment: 28 pages, 19 figure

Physical routes for the synthesis of kesterite

This paper provides an overview of the physical vapor technologies used to synthesize Cu2ZnSn(S,Se)4 thin films as absorber layers for photovoltaic applications. Through the years, CZT(S,Se) thin films have been fabricated using sequential stacking or co-sputtering of precursors as well as using sequential or co-evaporation of elemental sources, leading to high-efficient solar cells. In addition, pulsed laser deposition of composite targets and monograin growth by the molten salt method were developed as alternative methods for kesterite layers deposition. This review presents the growing increase of the kesterite-based solar cell efficiencies achieved over the recent years. A historical description of the main issues limiting this efficiency and of the experimental pathways designed to prevent or limit these issues is provided and discussed as well. Afinal section is dedicated to the description of promising process steps aiming at further improvements of solar cell efficiency, such as alkali doping and bandgap grading1. R Caballero and M León acknowledge financial support via the Spanish Ministry of Science, Innovation and Universities project (WINCOST, ENE2016-80788-C5-2-R) and thank H2020 EU Programme under the project INFINITE-CELL (H2020-MSCA-RISE-2017-777968). 2. S Canulescu and J Schou acknowledge the support from Innovation Fund Denmark. 3. D-H Kim acknowledges financial support via the DGIST R&D Program of the Ministry of Science and ICT, KOREA (18-BD-05). 4.C. Malerba acknowledges the support from the Italian Ministry of Economic development in the framework of the Operating Agreement with ENEA for the Research on the Electric System. 5.A Redinger acknowledges financial support via the FNR Attract program, Project : SUNSPOT, Nr.11244141. 6. E Saucedo thanks H2020 EU Programme under the projects STARCELL (H2020-NMBP-03-2016-720907) and INFINITE-CELL (H2020-MSCA-RISE-2017-777968), the Spanish Ministry of Science, Innovation and Universities for the IGNITE project (ENE2017-87671-C3-1-R), and the European Regional Development Funds (ERDF, FEDER Programa Competitivitat de Catalunya 2007–2013). IREC belong to the SEMS (Solar Energy Materials and Systems) Consolidated Research Group of the ‘Generalitat de Catalunya’ (Ref. 2017 SGR 862). 7. Taltech acknowledges financial support via the Estonian Ministry of Education and Research funding project IUT19-28 and the European Union Regional Development Fund, Project TK141. 8. B Vermang has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 Research and Innovation Programme (Grant Agreement No 715027