Architectures for maximum-sequence-length digital delta-sigma modulators

In this paper, we extend the idea developed in some of our earlier works of using output feedback to make the quantization step in a digital delta-sigma modulator (DDSM) appear prime. This maximizes the cycle lengths for constant inputs, spreading the quantization error over the maximum number of frequency terms, and consequently, minimizing the power per tone. We show how this concept can be applied to multibit higher order error-feedback modulators (EFMs). In addition, we show that the idea can be implemented in a class of single-quantizer DDSMs (SQ-DDSM) where STF (z) = z(-L) and NTF (z) = (1 - Z(-1))(L)

Influence of initial conditions on the fundamental periods of LFSR-dithered MASH digital delta-sigma modulators with constant inputs

A digital delta-sigma modulator (DDSM) with a constant input may produce a periodic output with a small fundamental period, resulting in strong tonal output behavior instead of the expected shaped white quantization noise. In practice, the problem is alleviated by dithering the DDSM. Pseudorandom dither generators based on linear feedback shift registers (LFSRs) are widely used to "break up" periodic cycles in DDSMs with constant inputs. Pseudorandom dither signals are themselves periodic and can lead to relatively short output sequences from dithered DDSMs. It is known that the fundamental period of the output signal depends not only on the input and the initial condition of the DDSM but also on the initial state of the LFSR. This brief shows that bad LFSR initial conditions can lead to ineffective dithering, producing short cycles and strong tonal behavior. Furthermore, it explains how to set the initial state of the DDSM as a function of the initial state of the LFSR in order to obtain a maximum-length dithered output

Hardware reduction in digital delta-sigma modulators via error masking - part II: SQ-DDSM

In this two-part paper, a design methodology for reduced-complexity digital delta-sigma modulators (DDSMs) based on error masking is presented. Rules for selecting the wordlengths of the stages in multistage architectures are elaborated. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation results confirm theoretical predictions. Part I addresses multistage noise-shaping DDSMs, whereas Part II focuses on single-quantizer DDSMs

Mathematical analysis of prime modulus quantizer MASH digital delta-sigma modulator

A MASH digital delta-sigma modulator (DDSM) is analyzed mathematically. It incorporates first-order error feedback modulators (EFM) which include prime modulus quantizers to guarantee a minimum sequence length M. The purpose of this analysis is to calculate the exact sequence length of the aforementioned MASH DDSM. We show that the sequence length for an lth-order member of this modulator family is M for all constant inputs, and for all initial conditions, where M is the sequence length of the constituent first-order prime modulus quantizer EFMs.

A low-power recursive I/Q signal generator and current driver for bioimpedance applications

This brief presents a power-efficient quadrature signal generator and current driver application-specific integrated circuit (ASIC) for bioimpedance measurements in an electrical impedance tomography system for monitoring lung function. The signal generator is realized by a digital recursive signal oscillator with the ability of generating quadrature signals over a wide frequency range. The generated in-phase signal is applied to a current driver. It uses a balanced current-mode feedback architecture that monitors the output current through a feedback loop to minimize common-mode voltage build-up at the injection site. The quadrature signals can be used for I/Q demodulation of the measured bioimpedance. The ASIC was designed in TSMC 65 nm technology occupying an area of 0.21 mm2. The current driver can generate up to 0.7 mA current up to 200 kHz and consumes 2.7 mW power using ±0.8 V supplies

Wandering spur suppression in a 4.9-GHz fractional-N frequency synthesizer

Fractional-N frequency synthesizers that use a digital Δ-Σ modulator (DDSM) to control the feedback divider can exhibit spurious tones that move about in the frequency domain; these are known colloquially as ``walking'' or wandering spurs. Building upon a theoretical explanation of the origin of wandering spurs, this article presents two methods to suppress them. It describes a 4.9-GHz 180-nm SiGe BiCMOS charge-pump phase-locked loop (CP-PLL) fractional-N frequency synthesizer platform with a divider controller that can function as: 1) a standard MASH 1-1-1; 2) a MASH 1-1-1 with high-amplitude dither; and 3) a MASH 1-1-1 with a modified third stage. Measurements confirm the effectiveness of the wandering spur suppression strategies

Prediction of phase noise and spurs in a nonlinear fractional-N frequency synthesizer

Integer boundary spurs appear in the passband of the loop response of fractional-N phase lock loops and are, therefore, a potentially significant component of the phase noise. In spite of measures guaranteeing spur-free modulator outputs, the interaction of the modulation noise from a divider controller with inevitable loop nonlinearities produces such spurs. This paper presents analytical predictions of the locations and amplitudes of the spurs and accompanying noise floor levels produced by interaction between a divider controller output and a PLL loop with a static nonlinearity. A key finding is that the spur locations and amplitudes can be estimated by using only the knowledge of the structure and pdf of the accumulated modulator noise and the nonlinearity. These predictions also offer new insights into why the spurs appear

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe

The Sigma-Delta Modulator as a Chaotic Nonlinear Dynamical System

The sigma-delta modulator is a popular signal amplitude quantization error (or noise) shaper used in oversampling analogue-to-digital and digital-to-analogue converter systems. The shaping of the noise frequency spectrum is performed by feeding back the quantization errors through a time delay element filter and feedback loop in the circuit, and by the addition of a possible stochastic dither signal at the quantizer. The aim in audio systems is to limit audible noise and distortions in the reconverted analogue signal. The formulation of the sigma-delta modulator as a discrete dynamical system provides a useful framework for the mathematical analysis of such a complex nonlinear system, as well as a unifying basis from which to consider other systems, from pseudorandom number generators to stochastic resonance processes, that yield equivalent formulations. The study of chaos and other complementary aspects of internal dynamical behaviour in previous research has left important issues unresolved. Advancement of this study is naturally facilitated by the dynamical systems approach. In this thesis, the general order feedback/feedforward sigma-delta modulator with multi-bit quantizer (no overload) and general input, is modelled and studied mathematically as a dynamical system. This study employs pertinent topological methods and relationships, which follow centrally from the symmetry of the circle map interpretation of the error state space dynamcis. The main approach taken is to reduce the nonlinear system into local or special case linear systems. Systems of sufficient structure are shown to often possess structured random, or random-like behaviour. An adaptation of Devaney's definition of chaos is applied to the model, and an extensive investigation of the conditions under which the associated chaos conditions hold or do not hold is carried out. This seeks, in part, to address the unresolved research issues. Chaos is shown to hold if all zeros of the noise transfer function lie outside the unit circle of radius two, provided the input is either periodic or persistently random (mod delta). When the filter satisfies a certain continuity condition, the conditions for chaos are extended, and more clear cut classifications emerge. Other specific chaos classifications are established. A study of the statistical properties of the error in dithered quantizers and sigma-delta modulators is pursued using the same state space model. A general treatment of the steady state error probability distribution is introduced, and results for predicting uniform steady state errors under various conditions are found. The uniformity results are applied to RPDF dithered systems to give conditions for a steady state error variance of delta squared over six. Numerical simulations support predictions of the analysis for the first-order case with constant input. An analysis of conditions on the model to obtain bounded internal stability or instability is conducted. The overall investigation of this thesis provides a theoretical approach upon which to orient future work, and initial steps of inquiry that can be advanced more extensively in the future

Dynamic element matching techniques for data converters

Analog to digital converter (ADC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in an ADC\u27s output. In this dissertation, two techniques for estimating an ADC\u27s output spectrum from the ADC\u27s transfer function are determined. These methods are compared to a symmetric power function and asymmetric power function approximations. Standard ADC performance metrics, such as SDR, SNDR, SNR, and SFDR, are also determined as a function of the ADC\u27s transfer function approximations. New dynamic element matching (DEM) flash ADCs are developed. An analysis of these DEM flash ADCs is developed and shows that these DEM algorithms improve an ADC\u27s performance. The analysis is also used to analyze several existing DEM ADC architectures; Digital to analog converter (DAC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in a DAC\u27s output. In this dissertation, an exact relationship between a DAC\u27s integral nonlinearity (INL) and its output spectrum is determined. Using this relationship, standard DAC performance metrics, such as SDR, SNDR, SNR, and SFDR, are calculated from the DAC\u27s transfer function. Furthermore, an iterative method is developed which determines an arbitrary DAC\u27s transfer function from observed output magnitude spectra. An analysis of DEM techniques for DACs, including the determination of several suitable metrics by which DEM techniques can be compared, is derived. The performance of a given DEM technique is related to standard DAC performance metrics, such as SDR, SNDR, and SFDR. Conditions under which DEM techniques can guarantee zero average INL and render the distortion due to mismatched components as white noise are developed. Several DEM circuits proposed in the literature are shown to be equivalent and have hardware efficient implementations based on multistage interconnection networks. Example DEM circuit topologies and their hardware efficient VLSI implementations are also presented