315 research outputs found
Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector
This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the\ud
proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 m CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is 80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is 121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3 ps rms
Multi-Phase Sub-Sampling Fractional-N PLL with soft loop switching for fast robust locking
This paper presents a low phase noise sub-sampling PLL (SSPLL) with multi-phase outputs. Automatic soft switching between the sub-sampling phase loop and frequency loop is proposed to improve robustness against perturbations and interferences that may cause a traditional SSPLL to lose lock. A quadrature LC oscillator with capacitive phase interpolation network is employed to generate multi-phase outputs, which are further utilized to achieve fractional-N frequency synthesis. Implemented in a 130nm CMOS technology, the SSPLL chip is able to achieve a measured in-band phase noise of -120 dBc/Hz and a measured integrated jitter of 209 fs at 2.4 GHz, while consuming 27.2 mW with 16 output phases. The measured reference spur and fractional spur level is -72 dBc and -49 dBc, respectively
Spur Reduction in Phase Lock Loop Using Charge Pump Current Matching Technique
A clock with high spectral purity is required in many applications. The spectral purity of the clock source is critical for the overall system performance. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high performance. The most important application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, ADCs to accurately define sampling moments and frequency synthesizers. The concept of PLL technique was first described in 1932. Since the invention of PLL, design of PLL has remained challenging because of requirements such as fast operation, low power consumption, less noisy electronic equipment's. Phase Frequency Detector (PFD), Charge pump and Voltage Controlled Oscillator (VCO) are the non-ideality components of PLL
Switched Capacitor Loop Filter ์ Source Switched Charge Pump ๋ฅผ ์ด์ฉํ Phase-Locked Loop ์ ์ค๊ณ
ํ์๋
ผ๋ฌธ(์์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022.2. ์ ๋๊ท .This thesis proposes a low integrated RMS jitter and low reference spur phase locked loop (PLL) using a switched capacitor loop filter and source switched charge pump. The PLL employs a single tunable charge pump which reduces current mis match across wide control voltage range and charge sharing effect to get high perfor mance of reference spur level. The switched capacitor loop filter is adopted to achieve insensitivity to temperature, supply voltage, and process variation of a resistor. The proposed PLL covers a wide frequency range and has a low integrated RMS jitter and low reference spur level to target various interface standards. The mechanism of switched capacitor loop filter and source switched charge pump is analyzed. Fabricated in 40 nm CMOS technology, the proposed analog PLL provides four phase for a quarter-rate transmitter, consumes 6.35 mW at 12 GHz using 750 MHz reference clock, and occupies an 0.008 mm2 with an integrated RMS jitter (10 kHz to 100 MHz) of 244.8 fs. As a result, the PLL achieves a figure of merit (FoM) of -244.2 dB with high power efficiency of 0.53 mW/GHz, and reference spur level is -60.3 dBc.๋ณธ ๋
ผ๋ฌธ์์๋ ๋ฎ์ RMS jitter ์ ๋ฎ์ ๋ ํผ๋ฐ์ค ์คํผ๋ฅผ ๊ฐ์ง๋ฉฐ ์ค์์น์ถ์ ๊ธฐ ๋ฃจํ ํํฐ์ ์์ค ์ค์์น ์ ํ ํํ๋ฅผ ์ด์ฉํ PLL ์ ์ ์ํ๋ค. ์ ์๋ PLL ์ ๋ ํผ๋ฐ์ค ์คํผ์ ์ฑ๋ฅ์ ์ํด ๋์ ์ปจํธ๋กค ์ ์์ ๋ฒ์ ๋์ ์ ๋ฅ์ ์ค์ฐจ๋ฅผ ์ค์ฌ์ฃผ๊ณ ์ ํ ๊ณต์ ํจ๊ณผ๋ฅผ ์ค์ฌ์ฃผ๋ ํ๋์ ์กฐ์ ๊ฐ๋ฅํ ์ ํ ํํ๋ฅผ ์ฌ์ฉํ์๋ค. ์ ํญ์ ์จ๋, ๊ณต๊ธ ์ ์, ๊ณต์ ๋ณํ์ ๋ฐ๋ฅธ ๋ฏผ๊ฐ๋๋ฅผ ๋ฎ์ถ๊ธฐ ์ํด ์ค์์น ์ถ์ ๊ธฐ ๋ฃจํ ํํฐ๊ฐ ์ฌ์ฉ๋์๋ค. ๋ค์ํ ์ธํฐํ์ด์ค ํ์ค์ ์ง์ํ๊ธฐ ์ํด ์ ์ํ๋ PLL ์ ๋์ ์ฃผํ์ ๋ฒ์๋ฅผ ์ง์ํ๊ณ ๋ฎ์ RMS jitter ์ ๋ฎ์ ๋ ํผ๋ฐ์ค ์คํผ๋ฅผ ๊ฐ๋๋ค. ์ค์์น ์ถ์ ๊ธฐ ๋ฃจํ ํํฐ์ ์์ค ์ค์์น ์ ํ ํํ์ ๋์ ์๋ฆฌ์ ๋ํด ๋ถ์ํ์๋ค. 40 nm CMOS ๊ณต์ ์ผ๋ก ์ ์๋์์ผ๋ฉฐ, ์ ์๋ ํ๋ก๋ quarter-rate ์ก์ ๊ธฐ๋ฅผ ์ํด 4 ๊ฐ์ phase ๋ฅผ ๋ง๋ค์ด๋ด๋ฉฐ 750 MHz ์ ๋ ํผ๋ฐ์ค ํด๋ฝ์ ์ด์ฉํ์ฌ 12 GHz ์์ 6.35 mW ์ power ๋ฅผ ์๋ชจํ๊ณ 0.008mm2 ์ ์ ํจ ๋ฉด์ ์ ์ฐจ์งํ๊ณ 10 kHz ๋ถํฐ 100 MHz ๊น์ง ์ ๋ถํ์ ๋์ RMS jitter ๊ฐ์ 244.8fs ์ด๋ค. ์ ์ํ๋ PLL ์ -244.2 dB ์ FoM, 0.53 mW/GHz ์ power ํจ์จ์ ๋ฌ์ฑํ์ผ๋ฉฐ ๋ ํผ๋ฐ์ค ์คํผ๋ -60.3 dBc ์ด๋คCHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 3
CHAPTER 2 BACKGROUNDS 4
2.1 CLOCK GENERATION IN SERIAL LINK 4
2.2 PLL BUILDING BLOCKS 6
2.2.1 OVERVIEW 6
2.2.2 PHASE FREQUENCY DETECTOR 7
2.2.3 CHARGE PUMP AND LOOP FILTER 9
2.2.4 VOLTAGE CONTROLLED OSCILLATOR 10
2.2.5 FREQUENCY DIVIDER 13
2.3 PLL LOOP ANALYSIS 15
CHAPTER 3 PLL WITH SWITCHED CAPACITOR LOOP FILTER AND SOURCE SWITCHED CHARGE PUMP 19
3.1 DESIGN CONSIDERATION 19
3.2 PROPOSED ARCHITECTURE 21
3.3 CIRCUIT IMPLEMENTATION 23
3.3.1 PHASE FREQUENCY DETECTOR 23
3.3.2 SOURCE SWITCHED CHARGE PUMP 26
3.3.3 SWITCHED CAPACITOR LOOP FILTER 30
3.3.4 VOLTAGE CONTROLLED OSCILLATOR 35
3.3.5 POST VCO AMPLIFIER 39
3.3.6 FREQUENCY DIVIDER 40
CHAPTER 4 MEASUREMENT RESULTS 43
4.1 CHIP PHOTOMICROGRAPH 43
4.2 MEASUREMENT SETUP 45
4.3 MEASURED PHASE NOISE AND REFERENCE SPUR 47
4.4 PERFORMANCE SUMMARY 50
CHAPTER 5 CONCLUSION 52
BIBLIOGRAPHY 53
์ด ๋ก 58์
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CMOS Signal Synthesizers for Emerging RF-to-Optical Applications
The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers.
This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented.
The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off.
The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space.
We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam
ULTRA-LOW-JITTER, MMW-BAND FREQUENCY SYNTHESIZERS BASED ON A CASCADED ARCHITECTURE
Department of Electrical EngineeringThis thesis presents an ultra-low-jitter, mmW-band frequency synthesizers based on a cascaded
architecture. First, the mmW-band frequency synthesizer based on a CP PLL is presented. At the
first stage, the CP PLL operating at GHz-band frequencies generated low-jitter output signals due
to a high-Q VCO. At the second stage, an ILFM operating at mmW-band frequencies has a wide
injection bandwidth, so that the jitter performance of the mmW-band output signals is determined
by the GHz-range PLL. The proposed ultra-low-jitter, mmW-band frequency synthesizer based on
a CP PLL, fabricated in a 65-nm CMOS technology, generated output signals from GHz-band
frequencies to mmW-band frequencies, achieving an RMS jitter of 206 fs and an IPN of ???31 dBc.
The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively.
However, due to a large in-band phase noise contribution of a PFD and a CP in the CP PLL, this
first stage was difficult to achieve an ultra-low in-band phase noise. Second, to improve the in-band
phase noise further, the mmW-band frequency synthesizer based on a digital SSPLL is presented.
At the first stage, the digital SSPLL operating at GHz-band frequencies generated ultra-low-jitter
output signals due to its sub-sampling operation and a high-Q GHz VCO. To minimize the
quantization noise of the voltage quantizer in the digital SSPLL, this thesis presents an OSVC as a
voltage quantizer while a small amount of power was consumed. The proposed ultra-low-jitter,
mmW-band frequency synthesizer fabricated in a 65-nm CMOS technology, generated output
signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 77 fs
and an IPN of ???40 dBc. The active silicon area and the total power consumption were 0.32 mm2 and
42 mW, respectively.clos
2.4 GHz Phase Locked Loop with DLL Based Spur Suppression Technique in 40nm CMOS
Phase locked loops (PLLs) are widely used as frequency synthesizers in modern communication systems because of the frequency accuracy and programmability of output frequency.
Reference spur is an issue of concern in the PLL design as it merges the interference into the desired signal band. This study focuses on the design of PLLs with low reference spurs level. A PLL with 2.4 GHz output frequency is implemented in TSMC 40nm CMOS technology using a 1.1V supply. A delay locked loop (DLL) is inserted in the phase locked loop as a multiple phase generator, in order to move the fundamental spur to higher frequency. The influence of errors inside the DLL due to CMOS process on the performance of spur suppression is also analyzed in this work. Two independent calibration systems, continuous time calibration and switch capacitor integrator based calibration for DLLโs errors are presented, to reduce the delay errors.
A spur reduction of 35 dB compared to a conventional structure is verified by the schematic simulation in Cadence
LOW-JITTER AND LOW-SPUR RING-OSCILLATOR-BASED PHASE-LOCKED LOOPS
Department of Electrical EngineeringIn recent years, ring-oscillator based clock generators have drawn a lot of attention due to the merits of high area efficiency, potentially wide tuning range, and multi-phase generation. However, the key challenge is how to suppress the poor jitter of ring oscillators. There have been many efforts to develop a ring-oscillator-based clock generator targeting very low-jitter performance. However, it remains difficult for conventional architectures to achieve both low RMS jitter and low levels of reference spurs concurrently while having a high multiplication factor. In this dissertation, a time-domain analysis is presented that provides an intuitive understanding of RMS jitter calculation of the clock generators from their phase-error correction mechanisms. Based on this analysis, we propose new designs of a ring-oscillator-based PLL that addresses the challenges of prior-art ring-based architectures.
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