315 research outputs found

    Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

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    This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the\ud proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 m CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is 80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is 121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3 ps rms

    Multi-Phase Sub-Sampling Fractional-N PLL with soft loop switching for fast robust locking

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    This paper presents a low phase noise sub-sampling PLL (SSPLL) with multi-phase outputs. Automatic soft switching between the sub-sampling phase loop and frequency loop is proposed to improve robustness against perturbations and interferences that may cause a traditional SSPLL to lose lock. A quadrature LC oscillator with capacitive phase interpolation network is employed to generate multi-phase outputs, which are further utilized to achieve fractional-N frequency synthesis. Implemented in a 130nm CMOS technology, the SSPLL chip is able to achieve a measured in-band phase noise of -120 dBc/Hz and a measured integrated jitter of 209 fs at 2.4 GHz, while consuming 27.2 mW with 16 output phases. The measured reference spur and fractional spur level is -72 dBc and -49 dBc, respectively

    Spur Reduction in Phase Lock Loop Using Charge Pump Current Matching Technique

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    A clock with high spectral purity is required in many applications. The spectral purity of the clock source is critical for the overall system performance. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high performance. The most important application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, ADCs to accurately define sampling moments and frequency synthesizers. The concept of PLL technique was first described in 1932. Since the invention of PLL, design of PLL has remained challenging because of requirements such as fast operation, low power consumption, less noisy electronic equipment's. Phase Frequency Detector (PFD), Charge pump and Voltage Controlled Oscillator (VCO) are the non-ideality components of PLL

    Switched Capacitor Loop Filter ์™€ Source Switched Charge Pump ๋ฅผ ์ด์šฉํ•œ Phase-Locked Loop ์˜ ์„ค๊ณ„

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    ํ•™์œ„๋…ผ๋ฌธ(์„์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2022.2. ์ •๋•๊ท .This thesis proposes a low integrated RMS jitter and low reference spur phase locked loop (PLL) using a switched capacitor loop filter and source switched charge pump. The PLL employs a single tunable charge pump which reduces current mis match across wide control voltage range and charge sharing effect to get high perfor mance of reference spur level. The switched capacitor loop filter is adopted to achieve insensitivity to temperature, supply voltage, and process variation of a resistor. The proposed PLL covers a wide frequency range and has a low integrated RMS jitter and low reference spur level to target various interface standards. The mechanism of switched capacitor loop filter and source switched charge pump is analyzed. Fabricated in 40 nm CMOS technology, the proposed analog PLL provides four phase for a quarter-rate transmitter, consumes 6.35 mW at 12 GHz using 750 MHz reference clock, and occupies an 0.008 mm2 with an integrated RMS jitter (10 kHz to 100 MHz) of 244.8 fs. As a result, the PLL achieves a figure of merit (FoM) of -244.2 dB with high power efficiency of 0.53 mW/GHz, and reference spur level is -60.3 dBc.๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ๋‚ฎ์€ RMS jitter ์™€ ๋‚ฎ์€ ๋ ˆํผ๋Ÿฐ์Šค ์Šคํผ๋ฅผ ๊ฐ€์ง€๋ฉฐ ์Šค์œ„์น˜์ถ•์ „๊ธฐ ๋ฃจํ”„ ํ•„ํ„ฐ์™€ ์†Œ์Šค ์Šค์œ„์น˜ ์ „ํ•˜ ํŽŒํ”„๋ฅผ ์ด์šฉํ•œ PLL ์„ ์ œ์•ˆํ•œ๋‹ค. ์ œ์•ˆ๋œ PLL ์€ ๋ ˆํผ๋Ÿฐ์Šค ์Šคํผ์˜ ์„ฑ๋Šฅ์„ ์œ„ํ•ด ๋„“์€ ์ปจํŠธ๋กค ์ „์••์˜ ๋ฒ”์œ„ ๋™์•ˆ ์ „๋ฅ˜์˜ ์˜ค์ฐจ๋ฅผ ์ค„์—ฌ์ฃผ๊ณ  ์ „ํ•˜ ๊ณต์œ  ํšจ๊ณผ๋ฅผ ์ค„์—ฌ์ฃผ๋Š” ํ•˜๋‚˜์˜ ์กฐ์ ˆ ๊ฐ€๋Šฅํ•œ ์ „ํ•˜ ํŽŒํ”„๋ฅผ ์‚ฌ์šฉํ•˜์˜€๋‹ค. ์ €ํ•ญ์˜ ์˜จ๋„, ๊ณต๊ธ‰ ์ „์••, ๊ณต์ • ๋ณ€ํ™”์— ๋”ฐ๋ฅธ ๋ฏผ๊ฐ๋„๋ฅผ ๋‚ฎ์ถ”๊ธฐ ์œ„ํ•ด ์Šค์œ„์น˜ ์ถ•์ „๊ธฐ ๋ฃจํ”„ ํ•„ํ„ฐ๊ฐ€ ์‚ฌ์šฉ๋˜์—ˆ๋‹ค. ๋‹ค์–‘ํ•œ ์ธํ„ฐํŽ˜์ด์Šค ํ‘œ์ค€์„ ์ง€์›ํ•˜๊ธฐ ์œ„ํ•ด ์ œ์•ˆํ•˜๋Š” PLL ์€ ๋„“์€ ์ฃผํŒŒ์ˆ˜ ๋ฒ”์œ„๋ฅผ ์ง€์›ํ•˜๊ณ  ๋‚ฎ์€ RMS jitter ์™€ ๋‚ฎ์€ ๋ ˆํผ๋Ÿฐ์Šค ์Šคํผ๋ฅผ ๊ฐ–๋Š”๋‹ค. ์Šค์œ„์น˜ ์ถ•์ „๊ธฐ ๋ฃจํ”„ ํ•„ํ„ฐ์™€ ์†Œ์Šค ์Šค์œ„์น˜ ์ „ํ•˜ ํŽŒํ”„์˜ ๋™์ž‘ ์›๋ฆฌ์— ๋Œ€ํ•ด ๋ถ„์„ํ•˜์˜€๋‹ค. 40 nm CMOS ๊ณต์ •์œผ๋กœ ์ œ์ž‘๋˜์—ˆ์œผ๋ฉฐ, ์ œ์•ˆ๋œ ํšŒ๋กœ๋Š” quarter-rate ์†ก์‹ ๊ธฐ๋ฅผ ์œ„ํ•ด 4 ๊ฐœ์˜ phase ๋ฅผ ๋งŒ๋“ค์–ด๋‚ด๋ฉฐ 750 MHz ์˜ ๋ ˆํผ๋Ÿฐ์Šค ํด๋ฝ์„ ์ด์šฉํ•˜์—ฌ 12 GHz ์—์„œ 6.35 mW ์˜ power ๋ฅผ ์†Œ๋ชจํ•˜๊ณ  0.008mm2 ์˜ ์œ ํšจ ๋ฉด์ ์„ ์ฐจ์ง€ํ•˜๊ณ  10 kHz ๋ถ€ํ„ฐ 100 MHz ๊นŒ์ง€ ์ ๋ถ„ํ–ˆ์„ ๋•Œ์˜ RMS jitter ๊ฐ’์€ 244.8fs ์ด๋‹ค. ์ œ์•ˆํ•˜๋Š” PLL ์€ -244.2 dB ์˜ FoM, 0.53 mW/GHz ์˜ power ํšจ์œจ์„ ๋‹ฌ์„ฑํ–ˆ์œผ๋ฉฐ ๋ ˆํผ๋Ÿฐ์Šค ์Šคํผ๋Š” -60.3 dBc ์ด๋‹คCHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUNDS 4 2.1 CLOCK GENERATION IN SERIAL LINK 4 2.2 PLL BUILDING BLOCKS 6 2.2.1 OVERVIEW 6 2.2.2 PHASE FREQUENCY DETECTOR 7 2.2.3 CHARGE PUMP AND LOOP FILTER 9 2.2.4 VOLTAGE CONTROLLED OSCILLATOR 10 2.2.5 FREQUENCY DIVIDER 13 2.3 PLL LOOP ANALYSIS 15 CHAPTER 3 PLL WITH SWITCHED CAPACITOR LOOP FILTER AND SOURCE SWITCHED CHARGE PUMP 19 3.1 DESIGN CONSIDERATION 19 3.2 PROPOSED ARCHITECTURE 21 3.3 CIRCUIT IMPLEMENTATION 23 3.3.1 PHASE FREQUENCY DETECTOR 23 3.3.2 SOURCE SWITCHED CHARGE PUMP 26 3.3.3 SWITCHED CAPACITOR LOOP FILTER 30 3.3.4 VOLTAGE CONTROLLED OSCILLATOR 35 3.3.5 POST VCO AMPLIFIER 39 3.3.6 FREQUENCY DIVIDER 40 CHAPTER 4 MEASUREMENT RESULTS 43 4.1 CHIP PHOTOMICROGRAPH 43 4.2 MEASUREMENT SETUP 45 4.3 MEASURED PHASE NOISE AND REFERENCE SPUR 47 4.4 PERFORMANCE SUMMARY 50 CHAPTER 5 CONCLUSION 52 BIBLIOGRAPHY 53 ์ดˆ ๋ก 58์„

    ULTRA-LOW-JITTER, MMW-BAND FREQUENCY SYNTHESIZERS BASED ON A CASCADED ARCHITECTURE

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    Department of Electrical EngineeringThis thesis presents an ultra-low-jitter, mmW-band frequency synthesizers based on a cascaded architecture. First, the mmW-band frequency synthesizer based on a CP PLL is presented. At the first stage, the CP PLL operating at GHz-band frequencies generated low-jitter output signals due to a high-Q VCO. At the second stage, an ILFM operating at mmW-band frequencies has a wide injection bandwidth, so that the jitter performance of the mmW-band output signals is determined by the GHz-range PLL. The proposed ultra-low-jitter, mmW-band frequency synthesizer based on a CP PLL, fabricated in a 65-nm CMOS technology, generated output signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 206 fs and an IPN of ???31 dBc. The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively. However, due to a large in-band phase noise contribution of a PFD and a CP in the CP PLL, this first stage was difficult to achieve an ultra-low in-band phase noise. Second, to improve the in-band phase noise further, the mmW-band frequency synthesizer based on a digital SSPLL is presented. At the first stage, the digital SSPLL operating at GHz-band frequencies generated ultra-low-jitter output signals due to its sub-sampling operation and a high-Q GHz VCO. To minimize the quantization noise of the voltage quantizer in the digital SSPLL, this thesis presents an OSVC as a voltage quantizer while a small amount of power was consumed. The proposed ultra-low-jitter, mmW-band frequency synthesizer fabricated in a 65-nm CMOS technology, generated output signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 77 fs and an IPN of ???40 dBc. The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively.clos

    2.4 GHz Phase Locked Loop with DLL Based Spur Suppression Technique in 40nm CMOS

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    Phase locked loops (PLLs) are widely used as frequency synthesizers in modern communication systems because of the frequency accuracy and programmability of output frequency. Reference spur is an issue of concern in the PLL design as it merges the interference into the desired signal band. This study focuses on the design of PLLs with low reference spurs level. A PLL with 2.4 GHz output frequency is implemented in TSMC 40nm CMOS technology using a 1.1V supply. A delay locked loop (DLL) is inserted in the phase locked loop as a multiple phase generator, in order to move the fundamental spur to higher frequency. The influence of errors inside the DLL due to CMOS process on the performance of spur suppression is also analyzed in this work. Two independent calibration systems, continuous time calibration and switch capacitor integrator based calibration for DLLโ€™s errors are presented, to reduce the delay errors. A spur reduction of 35 dB compared to a conventional structure is verified by the schematic simulation in Cadence

    LOW-JITTER AND LOW-SPUR RING-OSCILLATOR-BASED PHASE-LOCKED LOOPS

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    Department of Electrical EngineeringIn recent years, ring-oscillator based clock generators have drawn a lot of attention due to the merits of high area efficiency, potentially wide tuning range, and multi-phase generation. However, the key challenge is how to suppress the poor jitter of ring oscillators. There have been many efforts to develop a ring-oscillator-based clock generator targeting very low-jitter performance. However, it remains difficult for conventional architectures to achieve both low RMS jitter and low levels of reference spurs concurrently while having a high multiplication factor. In this dissertation, a time-domain analysis is presented that provides an intuitive understanding of RMS jitter calculation of the clock generators from their phase-error correction mechanisms. Based on this analysis, we propose new designs of a ring-oscillator-based PLL that addresses the challenges of prior-art ring-based architectures. This dissertation introduces a ring-oscillator-based PLL with the proposed fast phase-error correction (FPEC) technique, which emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). With the FPEC technique, the phase error of the voltage-controlled oscillator (VCO) is quickly removed, achieving ultra-low jitter. In addition, in the transfer function of the proposed architecture, an intrinsic integrator is involved since it is naturally based on a PLL topology. The proposed PLL can thus have low levels of reference spurs while maintaining high stability even for a large multiplication factor. Furthermore, it presents another design of a digital PLL embodying the FPEC technique (or FPEC DPLL). To overcome the problem of a conventional TDC, a low-power optimally-spaced (OS) TDC capable of effectively minimizing the quantization error is presented. In the proposed FPEC DPLL, background digital controllers continuously calibrate the decision thresholds and the gain of the error correction by the loop to be optimal, thus dramatically reducing the quantization error. Since the proposed architecture is implemented in a digital fashion, the variables defining the characteristics of the loop can be easily estimated and calibrated by digital calibrators. As a result, the performances of an ultra-low jitter and the figure-of-merit can be achieved.clos

    Low power/low voltage techniques for analog CMOS circuits

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