1,156 research outputs found
Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter
As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter
A Piecewise Linear Approximation D/A Converter for Small Format LCD Applications
Low power operation is a driving requirement for the advancement of portable consumer electronics. As products get smaller and have more functionality the device integration requirements get tighter. This is certainly true of small format LCD applications like PDAs and cell phones. Recent advances in LCD technology have allowed for advanced circuitry to be built on the glass. This allows for the unique opportunity to integrate the LCD column driver with other circuitry rather than the traditional flip chip mounting on the glass. The integration of these D/A converters with digital circuitry presents a new set of design considerations. These considerations allow for the exploration of non-traditional architectures and algorithms. This work will explore these design considerations in detail and present a novel algorithm for conversion as well as a system implementation of this algorithm. The system implementation is compared to a standard linear converter to weigh the relative advantages of each. A high performance dynamically biased amplifier is developed for use in the D/A converter. This amplifier has a high slew rate while consuming a small amount of quiescent power
NASA micromin computer Monthly progress letter, Jan. 1967
Microminiature circuit development for flight control computer
All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters
The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic Split-ADC calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the Split-ADC method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 Split-TI converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the Split-SAR method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples
Doctor of Philosophy
dissertationHigh speed wireless communication systems (e.g., long-term evolution (LTE), Wi-Fi) operate with high bandwidth and large peak-to-average power ratios (PAPRs). This is largely due to the use of orthogonal frequency division multiplexing (OFDM) modulation that is prevalent to maximize the spectral efficiency of the communication system. The power amplifier (PA) in the transmitter is the dominant energy consumer in the radio, largely because of the PAPR of the input signal. To reduce the energy consumption of the PA an amplifier that simultaneously achieves high efficiency and high linearity. Furthermore, to lower the cost for high volume production, it is desirable to achieve a complete System-on-Chip (SoC) integration. Linear amplifiers (e.g., Class-A, -B, -AB) are inefficient when amplifying signals with large PAPR that is associated by high peak-to-average modulation techniques such as LTE. OFDM. Switching amplifiers (e.g., Class-D, -E, -F) are very promising due to their high efficiency when compared to their linear amplifier counterparts. Linearization techniques for switching amplifiers have been intensively investigated due to their limited sensitivity to the input amplitude of the signal. Deep-submicron CMOS technology is mostly utilized for logic circuitry, and the Moore's law scaling of CMOS optimizes transistors to operate as high-speed and low-loss switches rather than high gain transistors. Hence, it is advantageous to use transistors in switching mode as switching amplifies and use high-speed digital logic circuitry to implement linearization systems and circuitry. In this work, several linearization architectures are investigated and demonstrated. An envelope elimination and restoration (EER) transmitter that comprises a class-E power amplifier and a 10-bit digital-to-analog converter (DAC) controlled current modulator is investigated. A pipelined switched-capacitor DAC is designed to control an open-loop transconductor that operates as a current modulator, modulating the amplitude of the current supplied to a class-E PA. Such a topology allows for increased filtering of the quantization noise that is problematic in most digital PAs (DPA). The proposed quadrature and multiphase architecture can avoid the bandwidth expansion and delay mismatch associated with polar PAs. The multiphase switched capacitor power amplifier (SCPA) was proposed after the quadrature SCPA and it significantly improves the power efficiency
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Energy and area efficient techniques for data converters
Data converters are ubiquitous building blocks of a signal chain. The rapid increase in
communication and connectivity devices presents new avenues for pushing the state of
the art analog to digital converters. Techniques for improving resolution, bandwidth,
linearity and bit-error rate, while reducing the power, energy and area is the motivation
for this research. This research focuses on achieving this goal by enabling circuit
techniques, architecture techniques and calibration methods. The following techniques
are proposed for enabling power, area and energy efficient analog to digital converter
techniques.
1. A capacitor switching scheme for successive approximation ADC is introduced to
enable 93.4% energy reduction and 75 % reduction in capacitor area as compared to a
conventional SAR ADCs.
2. Asynchronous correlated level shifting technique for improving current source linearity
and power supply rejection ratio of zero crossing based circuits is proposed. This
technique enables asynchronous ADC architectures for energy efficient system.
3. Unified gain enhancement model is proposed to catalogue gain enhancement techniques.
Class-A+ and Replicated Parallel Gain Enhancement (RPGe) amplifiers are
introduced as parallel gain enhancement techniques for switched capacitor circuits. A
prototype pipelined ADC using RPGE amplifier achieves 74.9 dB SNDR, 90.8 dB SFDR,
87 dB THD at 20 MS/s. Built in 1P4M 0.18 ÎŒm technology and operating at 1.3 V supply,
the ADC consumes 5.9 mW. The ADC occupies 3.06 sq. mm and has a figure of
merit of 65 fJ /conversion step. Extracted simulation results of the prototype pipeline
ADC using dynamic RPGE amplifier achieve 74 dB SNDR, 90 dB SFDR, and 85 dB
THD at 30 MS /s in a 0.18 ÎŒm process. The ADC consumes 6.6 mW from a 1.3 V
supply and achieves a figure of merit of 40 fJ/C-S.
4. A low-gain amplifier based V-T converter is utilized along with a TDC to replace
the function of flash ADC and the DAC references in a pipeline ADC. The simulated/
extracted performance of the chip is 12bit, 100 MHz in 65nm process while consuming
approximately 8-9 mA from 1 V supply.
5. A measurement technique for detecting and correcting bit-error rate in ADCs is proposed.
This multi-path ADC technique squares the bit-error rate of the ADC without
consuming additional analog power. The area increase is negligible compared to the
conventional modular redundancy techniques. This technique can be applied to digitally
detect and correct single event transients for ADCs. A three-path ADC can restore the
ADC performance independent of the input frequency and number of errors in a single
path.
6. LMS algorithm is used to estimate the VCO non-linearity by using the VCO as a
Nyquist ADC and utilizing a slow but accurate ADC. The simulated ADC performance
improves from 5 bits to 7.8 bits by using a second order fit to the VCO non-linearity
Low power, compact charge coupled device signal processing system
A variety of charged coupled devices (CCDs) for performing programmable correlation for preprocessing environmental sensor data preparatory to its transmission to the ground were developed. A total of two separate ICs were developed and a third was evaluated. The first IC was a CCD chirp z transform IC capable of performing a 32 point DFT at frequencies to 1 MHz. All on chip circuitry operated as designed with the exception of the limited dynamic range caused by a fixed pattern noise due to interactions between the digital and analog circuits. The second IC developed was a 64 stage CCD analog/analog correlator for performing time domain correlation. Multiplier errors were found to be less than 1 percent at designed signal levels and less than 0.3 percent at the measured smaller levels. A prototype IC for performing time domain correlation was also evaluated
Implementation of a 200 MSps 12-bit SAR ADC
Analog-to-digital converters (ADCs) with high conversion frequency, often based on pipelined architectures, are used for measuring instruments, wireless communication and video applications. Successive approximation register (SAR) converters offer a compact and power efficient alternative but the conversion speed is typically designed for lower frequencies. In this thesis a low-power 12-bit 200 MSps SAR ADC based on charge redistribution was designed for a 28 nm CMOS technology. The proposed design uses an efficient SAR algorithm (merged capacitor switching procedure) to reduce power consumption due to capacitor charging by 88 % compared to a conventional design, as well as reducing the total capacitor area by half. Sampling switches were bootstrapped for increased linearity compared to simple transmission gates. Another feature of the low power design is a fully-dynamic comparator which does not require a preamplifier. Pre-layout simulations of the SAR ADC with 800 MHz input frequency shows an SNDR of 64.8 dB, corresponding to an ENOB of 10.5, and an SFDR of 75.3 dB. The total power consumption is 1.77 mW with an estimated value of 500 W for the unimplemented digital logic. Calculation of the Schreier figure-of-merit was done with an input signal at the Nyquist frequency. The simulated SNDR, SFDR and power equals 69.5 dB, 77.3 dB and 1.9 mW respectively, corresponding to a figure-of merit of 176.6 dB.FrÄn analogt till digitalt - snabba och strömsnÄla omvandlare Dagens digitala samhÀlle stÀller höga krav pÄ prestanda och effektivitet. I samarbete med Ericsson i Lund har en krets för signalomvandling utvecklats. Genom smart design uppnÄs hög hastighet och lÄg strömförbrukning som ligger i forskningens framkant. FrÄn analogt till digitalt Ett viktigt byggblock för telekommunikation och videoapplikationer Àr sÄ kallade A/D-omvandlare, som översÀtter mellan analoga signaler (till exempel ljud) och digitala signaler bestÄende av ettor och nollor. En vÀldigt effektiv metod för A/D-omvandling bygger pÄ sÄ kallad successiv approximation. Metoden innebÀr att signalen som ska omvandlas jÀmförs med en referensnivÄ, som stegvis justeras för att nÀrma sig signalens vÀrde. Till slut har man en tillrÀckligt god uppskattning av vÀrdet som ska mÀtas. Just en sÄdan omvandlare har utvecklats med höga krav pÄ hastighet och energiförbrukning. Detta gjordes genom datorsimuleringar av modeller som beskriver kretsen. ReferensnivÄn skapas ofta genom att styra ett nÀtverk som lagrar elektrisk laddning. Omvandlingens noggrannhet, eller upplösning, beror pÄ hur mÄnga nivÄer som finns tillgÀngliga det vill sÀga hur nÀra signalens vÀrde man kan komma. I den designade kretsen finns hela 4096 nivÄer! Det finns mÄnga kÀllor till osÀkerhet i systemet, bland annat hur exakta referensnivÄerna Àr och hur bra jÀmförelsen med insignalen kan göras. Eftersom dessa eventuellt kan leda till en försÀmring av omvandlingens noggrannhet mÄste alla delar i kretsen utformas med detta i Ätanke. Höga hastigheter Eftersom det krÀvs mÄnga steg för referensnivÄn att nÀrma sig signalens vÀrde Àr den maximala omvandlingshastigheten ofta begrÀnsad. Med teknikens utveckling öppnas nya möjligheter i takt med att mikrochippens enskilda komponenter blir snabbare. Modern forskning visar att omvandlare baserade pÄ successiv approximation kan uppnÄ hastigheter pÄ flera miljoner mÀtvÀrden varje sekund, vilket Àven den utvecklade kretsen klarar av. Effektiv design Nya metoder för successiv approximation möjliggör stora besparingar nÀr det gÀller effektförbrukning, till exempel genom att effektivisera upp- och urladdningen av nÀtverket. Genom smÄ Àndringar kunde nÀtverkets energiförbrukning minskas med över 90 % samtidigt som dess area halverades. Eftersom produktionskostnaden för integrerade kretsar Àr hög medför varje minskning av kretsens area att kostnaden sjunker
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