A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Robust Convergence of Power Flow using Tx Stepping Method with Equivalent Circuit Formulation

Robust solving of critical large power flow cases (with 50k or greater buses) forms the backbone of planning and operation of any large connected power grid. At present, reliable convergence with applications of existing power flow tools to large power systems is contingent upon a good initial guess for the system state. To enable robust convergence for large scale systems starting with an arbitrary initial guess, we extend our equivalent circuit formulation for power flow analysis to include a novel continuation method based on transmission line (Tx) stepping. While various continuation methods have been proposed for use with the traditional PQV power flow formulation, these methods have either failed to completely solve the problem or have resulted in convergence to a low voltage solution. The proposed Tx Stepping method in this paper demonstrates robust convergence to the high voltage solution from an arbitrary initial guess. Example systems, including 75k+ bus test cases representing different loading and operating conditions for Eastern Interconnection of the U.S. power grid, are solved from arbitrary initial guesses.Interconnection of the U.S. power grid, are solved from arbitrary initial guesses

The Configurable SAT Solver Challenge (CSSC)

It is well known that different solution strategies work well for different types of instances of hard combinatorial problems. As a consequence, most solvers for the propositional satisfiability problem (SAT) expose parameters that allow them to be customized to a particular family of instances. In the international SAT competition series, these parameters are ignored: solvers are run using a single default parameter setting (supplied by the authors) for all benchmark instances in a given track. While this competition format rewards solvers with robust default settings, it does not reflect the situation faced by a practitioner who only cares about performance on one particular application and can invest some time into tuning solver parameters for this application. The new Configurable SAT Solver Competition (CSSC) compares solvers in this latter setting, scoring each solver by the performance it achieved after a fully automated configuration step. This article describes the CSSC in more detail, and reports the results obtained in its two instantiations so far, CSSC 2013 and 2014

Mixed-Signal Testability Analysis for Data-Converter IPs

In this paper, a new procedure to derive testability measures is presented. Digital testability can be calculated by means of probability, while in analog it is possible to calculate testability using impedance values. Although attempts have been made to reach compatibility, matching was somewhat arbitrary and therefore not necessarily compatible. The concept of the new approach is that digital and analog can be integrated in a more consistent way. More realistic testability figures are obtained, which makes testability of true mixed-signal systems and circuits feasible. To verify the results, our method is compared with a sensitivity analysis, for a simple 3-bit ADC