754 research outputs found
Memristor nanodevice for unconventional computing:review and applications
A memristor is a two-terminal nanodevice that its properties attract a wide
community of researchers from various domains such as physics, chemistry,
electronics, computer and neuroscience.The simple structure for manufacturing,
small scalability, nonvolatility and potential of using inlow power platforms
are outstanding characteristics of this emerging nanodevice. In this report,we
review a brief literature of memristor from mathematic model to the physical
realization. Wediscuss different classes of memristors based on the material
used for its manufacturing. Thepotential applications of memristor are
presented and a wide domain of applications are explainedand classified
Material Targets for Scaling All Spin Logic
All-spin logic devices are promising candidates to augment and complement
beyond-CMOS integrated circuit computing due to non-volatility, ultra-low
operating voltages, higher logical efficiency, and high density integration.
However, the path to reach lower energy-delay product performance compared to
CMOS transistors currently is not clear. We show that scaling and engineering
the nanoscale magnetic materials and interfaces is the key to realizing spin
logic devices that can surpass energy-delay performance of CMOS transistors.
With validated stochastic nano-magnetic and vector spin transport numerical
models, we derive the target material and interface properties for the
nanomagnets and channels. We identified promising new directions for material
engineering/discovery focusing on systematic scaling of magnetic anisotropy
(Hk) with saturation magnetization (Ms), use of perpendicular magnetic
anisotropy, and interface spin mixing conductance of ferromagnet/spin channel
interface (Gmix). We provide systematic targets for scaling spin logic
energy-delay product toward a 2 aJ.ns energy-delay product, comprehending the
stochastic noise for nanomagnets.Comment: 21 pages, 8 figure
Spin torque building blocks
The discovery of the spin torque effect has made magnetic nanodevices
realistic candidates for active elements of memory devices and applications.
Magnetoresistive effects allow the read-out of increasingly small magnetic
bits, and the spin torque provides an efficient tool to manipulate - precisely,
rapidly and at low energy cost - the magnetic state, which is in turn the
central information medium of spintronic devices. By keeping the same magnetic
stack, but by tuning a device's shape and bias conditions, the spin torque can
be engineered to build a variety of advanced magnetic nanodevices. Here we show
that by assembling these nanodevices as building blocks with different
functionalities, novel types of computing architectures can be envisisaged. We
focus in particular on recent concepts such as magnonics and spintronic neural
networks
Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing
Present day computers expend orders of magnitude more computational resources
to perform various cognitive and perception related tasks that humans routinely
perform everyday. This has recently resulted in a seismic shift in the field of
computation where research efforts are being directed to develop a
neurocomputer that attempts to mimic the human brain by nanoelectronic
components and thereby harness its efficiency in recognition problems. Bridging
the gap between neuroscience and nanoelectronics, this paper attempts to
provide a review of the recent developments in the field of spintronic device
based neuromorphic computing. Description of various spin-transfer torque
mechanisms that can be potentially utilized for realizing device structures
mimicking neural and synaptic functionalities is provided. A cross-layer
perspective extending from the device to the circuit and system level is
presented to envision the design of an All-Spin neuromorphic processor enabled
with on-chip learning functionalities. Device-circuit-algorithm co-simulation
framework calibrated to experimental results suggest that such All-Spin
neuromorphic systems can potentially achieve almost two orders of magnitude
energy improvement in comparison to state-of-the-art CMOS implementations.Comment: The paper will appear in a future issue of Applied Physics Review
Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic
A threshold logic gate (TLG) performs weighted sum of multiple inputs and
compares the sum with a threshold. We propose Spin-Memeristor Threshold Logic
(SMTL) gates, which employ memristive cross-bar array (MCA) to perform
current-mode summation of binary inputs, whereas, the low-voltage
fast-switching spintronic threshold devices (STD) carry out the threshold
operation in an energy efficient manner. Field programmable SMTL gate arrays
can operate at a small terminal voltage of ~50mV, resulting in ultra-low power
consumption in gates as well as programmable interconnect networks. We evaluate
the performance of SMTL using threshold logic synthesis. Results for common
benchmarks show that SMTL based programmable logic hardware can be more than
100x energy efficient than state of the art CMOS FPGA.Comment: this paper is submitted to IEEE Transactions on Nanotechnology. It is
currently under revie
Shape-based Magnetic Domain Wall Drift for an Artificial Spintronic Leaky Integrate-and-Fire Neuron
Spintronic devices based on domain wall (DW) motion through ferromagnetic
nanowire tracks have received great interest as components of neuromorphic
information processing systems. Previous proposals for spintronic artificial
neurons required external stimuli to perform the leaking functionality, one of
the three fundamental functions of a leaky integrate-and-fire (LIF) neuron. The
use of this external magnetic field or electrical current stimulus results in
either a decrease in energy efficiency or an increase in fabrication
complexity. In this work, we modify the shape of previously demonstrated
three-terminal magnetic tunnel junction neurons to perform the leaking
operation without any external stimuli. The trapezoidal structure causes
shape-based DW drift, thus intrinsically providing the leaking functionality
with no hardware cost. This LIF neuron therefore promises to advance the
development of spintronic neural network crossbar arrays
Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition
We present a new circuit for non-Boolean recognition of binary images.
Employing all-spin logic (ASL) devices, we design logic comparators and
non-Boolean decision blocks for compact and efficient computation. By
manipulation of fan-in number in different stages of the circuit, the structure
can be extended for larger training sets or larger images. Operating based on
the mainly similarity idea, the system is capable of constructing a mean image
and compare it with a separate input image within a short decision time. Taking
advantage of the non-volatility of ASL devices, the proposed circuit is capable
of hybrid memory/logic operation. Compared with existing CMOS pattern
recognition circuits, this work achieves a smaller footprint, lower power
consumption, faster decision time and a lower operational voltage. To the best
of our knowledge, this is the first fully spin-based complete pattern
recognition circuit demonstrated using spintronic devices.Comment: This article is accepted to appear in IEEE Transactions on
Nanotechnolog
A Probability-Density Function Approach to Capture the Stochastic Dynamics of the Nanomagnet and Impact on Circuit Performance
In this paper we systematically evaluate the variation in the reversal delay
of a nanomagnet driven by a longitudinal spin current while under the influence
of thermal noise. We then use the results to evaluate the performance of an
All-Spin-Logic (ASL) circuit. First, we review and expand on the physics of
previously-published analytical models on stochastic nanomagnet switching. The
limits of previously established models are defined and it is shown that these
models are valid for nanomagnet reversal times < 200 ps. Second, the insight
obtained from previous models allows us to represent the probability density
function (PDF) of the nanomagnet switching delay using the double exponential
function of the Frechet distribution. The PDF of a single nanomagnet is
extended to more complex nanomagnet circuit configurations. It is shown that
the delay-variation penalty incurred by nanomagnets arranged in parallel
configuration is dwarfed by the average delay increase for nanomagnets arranged
in a series configuration. Finally, we demonstrate the impact of device-level
performance variation on the circuit behavior using ASL logic gates. While the
analysis presented in this paper uses an ASL-AND gate as the prototype
switching circuit in the spin domain, the physical concepts are generic and can
be extended to any complex spin-based circuit
SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks
In this paper, a spintronic neuromorphic reconfigurable Array (SNRA) is
developed to fuse together power-efficient probabilistic and in-field
programmable deterministic computing during both training and evaluation phases
of restricted Boltzmann machines (RBMs). First, probabilistic spin logic
devices are used to develop an RBM realization which is adapted to construct
deep belief networks (DBNs) having one to three hidden layers of size 10 to 800
neurons each. Second, we design a hardware implementation for the contrastive
divergence (CD) algorithm using a four-state finite state machine capable of
unsupervised training in N+3 clocks where N denotes the number of neurons in
each RBM. The functionality of our proposed CD hardware implementation is
validated using ModelSim simulations. We synthesize the developed Verilog HDL
implementation of our proposed test/train control circuitry for various DBN
topologies where the maximal RBM dimensions yield resource utilization ranging
from 51 to 2,421 lookup tables (LUTs). Next, we leverage spin Hall effect
(SHE)-magnetic tunnel junction (MTJ) based non-volatile LUTs circuits as an
alternative for static random access memory (SRAM)-based LUTs storing the
deterministic logic configuration to form a reconfigurable fabric. Finally, we
compare the performance of our proposed SNRA with SRAM-based configurable
fabrics focusing on the area and power consumption induced by the LUTs used to
implement both CD and evaluation modes. The results obtained indicate more than
80% reduction in combined dynamic and static power dissipation, while achieving
at least 50% reduction in device count.Comment: 8 page
Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking
Multiple logic devices are presently under study within the Nanoelectronic
Research Initiative (NRI) to carry the development of integrated circuits
beyond the CMOS roadmap. Structure and operational principles of these devices
are described. Theories used for benchmarking these devices are overviewed, and
a general methodology is described for consistent estimates of the circuit
area, switching time and energy. The results of the comparison of the NRI logic
devices using these benchmarks are presented.Comment: 91 pages, 67 figures, 11 tables. Related to the conference
presentation D. Nikonov and I. Young, Uniform Methodology for Benchmarking
Beyond-CMOS Logic Devices, Proceedings of IEDM, 25.4 (2012
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