Notes About Spiking Neural P Systems

Spiking neural P systems (SN P systems, for short) are much investigated in the last years in membrane computing, but still many open problems and research topics are open in this area. Here, we first recall two such problems (both related to neural biology) from. One of them asks to build an SN P system able to store a number, and to provide it to a reader without losing it, so that the number is available for a further reading. We build here such a memory module and we discuss its extension to model/implement more general operations, specific to (simple) data bases. Then, we formulate another research issue, concerning pattern recognition in terms of SN P systems. In the context, we define a recent version of SN P systems, enlarged with rules able to request spikes from the environment; based on this version, so-called SN dP systems were recently introduced, extending to neural P systems the idea of a distributed dP automaton. Some details about such devices are also given, as a further invitation to the reader to this area of research.Junta de Andalucía P08 – TIC 0420

Spiking Neural P Systems: A Short Introduction and New Normal Forms

Spiking neural P systems are a class of P systems inspired from the way the neurons communicate with each other by means of electrical impulses (called \spikes"). In the few years since this model was introduced, many results related to the computing power and e ciency of these computing devices were reported. The present paper quickly surveys the basic ideas of this research area and the basic results, then, as typical proofs about the universality of spiking neural P systems, we present some new normal forms for them. Speci cally, we consider a natural restriction in the architecture of a spiking neural P system, to have neurons of a small number of types (i.e., using a small number of sets of rules). We prove that three types of neurons are su cient in order to generate each recursively enumerable set of numbers as the distance between the rst two spikes emitted by the system; the problem remains open for accepting SN P systems. The paper ends with the complete bibliography of this domain, at the level of April 2009.Ministerio de Educación y Ciencia TIN2006-13452Junta de Andalucía P08-TIC-0420

Sparse-matrix Representation of Spiking Neural P Systems for GPUs

Current parallel simulation algorithms for Spiking Neural P (SNP) systems are based on a matrix representation. This helps to harness the inherent parallelism in algebraic operations, such as vector-matrix multiplication. Although it has been convenient for the rst parallel simulators running on Graphics Processing Units (GPUs), such as CuSNP, there are some bottlenecks to cope with. For example, matrix representation of SNP systems with a low-connectivity-degree graph lead to sparse matrices, i.e. containing more zeros than actual values. Having to deal with sparse matrices downgrades the performance of the simulators because of wasting memory and time. However, sparse matrices is a known problem on parallel computing with GPUs, and several solutions and algorithms are available in the literature. In this paper, we brie y analyse some of these ideas and apply them to represent some variants of SNP systems. We also conclude which variant better suit a sparse-matrix representation

A Survey of Spiking Neural Network Accelerator on FPGA

Due to the ability to implement customized topology, FPGA is increasingly used to deploy SNNs in both embedded and high-performance applications. In this paper, we survey state-of-the-art SNN implementations and their applications on FPGA. We collect the recent widely-used spiking neuron models, network structures, and signal encoding formats, followed by the enumeration of related hardware design schemes for FPGA-based SNN implementations. Compared with the previous surveys, this manuscript enumerates the application instances that applied the above-mentioned technical schemes in recent research. Based on that, we discuss the actual acceleration potential of implementing SNN on FPGA. According to our above discussion, the upcoming trends are discussed in this paper and give a guideline for further advancement in related subjects