25,371 research outputs found
A 96-Channel FPGA-based Time-to-Digital Converter
We describe an FPGA-based, 96-channel, time-to-digital converter (TDC)
intended for use with the Central Outer Tracker (COT) in the CDF Experiment at
the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC
cards, each serving 96 wires of the chamber. The TDC is physically configured
as a 9U VME card. The functionality is almost entirely programmed in firmware
in two Altera Stratix FPGA's. The special capabilities of this device are the
availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and
abundant memory. The TDC system operates with an input resolution of 1.2 ns.
Each input can accept up to 7 hits per collision. The time-to-digital
conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and
filling a circular memory; the memory addresses of logical transitions (edges)
in the input data are then translated into the time of arrival and width of the
COT pulses. Memory pipelines with a depth of 5.5 s allow deadtime-less
operation in the first-level trigger. The TDC VME interface allows a 64-bit
Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47
Mbytes/sec. The TDC also contains a separately-programmed data path that
produces prompt trigger data every Tevatron crossing. The full TDC design and
multi-card test results are described. The physical simplicity ensures
low-maintenance; the functionality being in firmware allows reprogramming for
other applications.Comment: 32 pages, 13 figure
Real Time Animation of Virtual Humans: A Trade-off Between Naturalness and Control
Virtual humans are employed in many interactive applications using 3D virtual environments, including (serious) games. The motion of such virtual humans should look realistic (or ‘natural’) and allow interaction with the surroundings and other (virtual) humans. Current animation techniques differ in the trade-off they offer between motion naturalness and the control that can be exerted over the motion. We show mechanisms to parametrize, combine (on different body parts) and concatenate motions generated by different animation techniques. We discuss several aspects of motion naturalness and show how it can be evaluated. We conclude by showing the promise of combinations of different animation paradigms to enhance both naturalness and control
CSGNet: Neural Shape Parser for Constructive Solid Geometry
We present a neural architecture that takes as input a 2D or 3D shape and
outputs a program that generates the shape. The instructions in our program are
based on constructive solid geometry principles, i.e., a set of boolean
operations on shape primitives defined recursively. Bottom-up techniques for
this shape parsing task rely on primitive detection and are inherently slow
since the search space over possible primitive combinations is large. In
contrast, our model uses a recurrent neural network that parses the input shape
in a top-down manner, which is significantly faster and yields a compact and
easy-to-interpret sequence of modeling instructions. Our model is also more
effective as a shape detector compared to existing state-of-the-art detection
techniques. We finally demonstrate that our network can be trained on novel
datasets without ground-truth program annotations through policy gradient
techniques.Comment: Accepted at CVPR-201
Qubit Data Structures for Analyzing Computing Systems
Qubit models and methods for improving the performance of software and
hardware for analyzing digital devices through increasing the dimension of the
data structures and memory are proposed. The basic concepts, terminology and
definitions necessary for the implementation of quantum computing when
analyzing virtual computers are introduced. The investigation results
concerning design and modeling computer systems in a cyberspace based on the
use of two-component structure are presented.Comment: 9 pages,4 figures, Proceeding of the Third International Conference
on Data Mining & Knowledge Management Process (CDKP 2014
Simple and Effective Type Check Removal through Lazy Basic Block Versioning
Dynamically typed programming languages such as JavaScript and Python defer
type checking to run time. In order to maximize performance, dynamic language
VM implementations must attempt to eliminate redundant dynamic type checks.
However, type inference analyses are often costly and involve tradeoffs between
compilation time and resulting precision. This has lead to the creation of
increasingly complex multi-tiered VM architectures.
This paper introduces lazy basic block versioning, a simple JIT compilation
technique which effectively removes redundant type checks from critical code
paths. This novel approach lazily generates type-specialized versions of basic
blocks on-the-fly while propagating context-dependent type information. This
does not require the use of costly program analyses, is not restricted by the
precision limitations of traditional type analyses and avoids the
implementation complexity of speculative optimization techniques.
We have implemented intraprocedural lazy basic block versioning in a
JavaScript JIT compiler. This approach is compared with a classical flow-based
type analysis. Lazy basic block versioning performs as well or better on all
benchmarks. On average, 71% of type tests are eliminated, yielding speedups of
up to 50%. We also show that our implementation generates more efficient
machine code than TraceMonkey, a tracing JIT compiler for JavaScript, on
several benchmarks. The combination of implementation simplicity, low
algorithmic complexity and good run time performance makes basic block
versioning attractive for baseline JIT compilers
A path planning and path-following control framework for a general 2-trailer with a car-like tractor
Maneuvering a general 2-trailer with a car-like tractor in backward motion is
a task that requires significant skill to master and is unarguably one of the
most complicated tasks a truck driver has to perform. This paper presents a
path planning and path-following control solution that can be used to
automatically plan and execute difficult parking and obstacle avoidance
maneuvers by combining backward and forward motion. A lattice-based path
planning framework is developed in order to generate kinematically feasible and
collision-free paths and a path-following controller is designed to stabilize
the lateral and angular path-following error states during path execution. To
estimate the vehicle state needed for control, a nonlinear observer is
developed which only utilizes information from sensors that are mounted on the
car-like tractor, making the system independent of additional trailer sensors.
The proposed path planning and path-following control framework is implemented
on a full-scale test vehicle and results from simulations and real-world
experiments are presented.Comment: Preprin
APEnet+: a 3D toroidal network enabling Petaflops scale Lattice QCD simulations on commodity clusters
Many scientific computations need multi-node parallelism for matching up both
space (memory) and time (speed) ever-increasing requirements. The use of GPUs
as accelerators introduces yet another level of complexity for the programmer
and may potentially result in large overheads due to the complex memory
hierarchy. Additionally, top-notch problems may easily employ more than a
Petaflops of sustained computing power, requiring thousands of GPUs
orchestrated with some parallel programming model. Here we describe APEnet+,
the new generation of our interconnect, which scales up to tens of thousands of
nodes with linear cost, thus improving the price/performance ratio on large
clusters. The project target is the development of the Apelink+ host adapter
featuring a low latency, high bandwidth direct network, state-of-the-art wire
speeds on the links and a PCIe X8 gen2 host interface. It features hardware
support for the RDMA programming model and experimental acceleration of GPU
networking. A Linux kernel driver, a set of low-level RDMA APIs and an OpenMPI
library driver are available, allowing for painless porting of standard
applications. Finally, we give an insight of future work and intended
developments
- …