7 research outputs found
Abstract State Machines 1988-1998: Commented ASM Bibliography
An annotated bibliography of papers which deal with or use Abstract State
Machines (ASMs), as of January 1998.Comment: Also maintained as a BibTeX file at http://www.eecs.umich.edu/gasm
Automatic Datapath Abstraction Of Pipelined Circuits
Pipelined circuits operate as an assembly line that starts processing new instructions while older ones
continue execution. Control properties specify the correct behaviour of the pipeline with respect to
how it handles the concurrency between instructions. Control properties stand out as one of the most
challenging aspects of pipelined circuit verification. Their verification depends on the datapath and
memories, which in practice account for the largest part of the state space of the circuit. To alleviate
the state explosion problem, abstraction of memories and datapath becomes mandatory. This thesis
provides a methodology for an efficient abstraction of the datapath under all possible control-visible
behaviours. For verification of control properties, the abstracted datapath is then substituted in place
of the original one and the control circuitry is left unchanged. With respect to control properties, the
abstraction is shown conservative by both language containment and simulation.
For verification of control properties, the pipeline datapath is represented by a network of registers,
unrestricted combinational datapath blocks and muxes. The values flowing through the datapath are
called parcels. The control is the state machine that steers the parcels through the network. As parcels
travel through the pipeline, they undergo transformations through the datapath blocks. The control-
visible results of these transformations fan-out into control variables which in turn influence the next
stage the parcels are transferred to by the control. The semantics of the datapath is formalized as a
labelled transition system called a parcel automaton. Parcel automata capture the set of all control
visible paths through the pipeline and are derived without the need of reachability analysis of the
original pipeline. Datapath abstraction is defined using familiar concepts such as language containment
or simulation. We have proved results that show that datapath abstraction leads to pipeline abstraction.
Our approach has been incorporated into a practical algorithm that yields directly the abstract parcel
automaton, bypassing the construction of the concrete parcel automaton. The algorithm uses a SAT
solver to generate incrementally all possible control visible behaviours of the pipeline datapath. Our
largest case study is a 32-bit two-wide superscalar OpenRISC microprocessor written in VHDL, where
it reduced the size of the implementation from 35k gates to 2k gates in less than 10 minutes while using
less than 52MB of memory
Dynamically reconfigurable asynchronous processor
The main design requirements for today's mobile applications are:
路 high throughput performance.
路 high energy efficiency.
路 high programmability.
Until now, the choice of platform has often been limited to Application-Specific
Integrated Circuits (ASICs), due to their best-of-breed performance and power
consumption. The economies of scale possible with these high-volume markets have
traditionally been able to hide the high Non-Recurring Engineering (NRE) costs
required for designing and fabricating new ASICs. However, with the NREs and
design time escalating with each generation of mobile applications, this practice may
be reaching its limit.
Designers today are looking at programmable solutions, so that they can respond
more rapidly to changes in the market and spread costs over several generations of
mobile applications. However, there have been few feasible alternatives to ASICs:
Digital Signals Processors (DSPs) and microprocessors cannot meet the throughput
requirements, whereas Field-Programmable Gate Arrays (FPGAs) require too much
area and power.
Coarse-grained dynamically reconfigurable architectures offer better solutions for
high throughput applications, when power and area considerations are taken into
account. One promising example is the Reconfigurable Instruction Cell Array
(RICA). RICA consists of an array of cells with an interconnect that can be
dynamically reconfigured on every cycle. This allows quite complex datapaths to be
rendered onto the fabric and executed in a single configuration - making these
architectures particularly suitable to stream processing. Furthermore, RICA can be
programmed from C, making it a good fit with existing design methodologies.
However the RICA architecture has a drawback: poor scalability in terms of area and
power. As the core gets bigger, the number of sequential elements in the array must
be increased significantly to maintain the ability to achieve high throughputs through
pipelining. As a result, a larger clock tree is required to synchronise the increased
number of sequential elements. The clock tree therefore takes up a larger percentage
of the area and power consumption of the core.
This thesis presents a novel Dynamically Reconfigurable Asynchronous Processor
(DRAP), aimed at high-throughput mobile applications. DRAP is based on the RICA
architecture, but uses asynchronous design techniques - methods of designing digital
systems without clocks. The absence of a global clock signal makes DRAP more
scalable in terms of power and area overhead than its synchronous counterpart.
The DRAP architecture maintains most of the benefits of custom asynchronous
design, whilst also providing programmability via conventional high-level languages.
Results show that the DRAP processor delivers considerably lower power
consumption when compared to a market-leading Very Long Instruction Word
(VLIW) processor and a low-power ARM processor. For example, DRAP resulted in
a reduction in power consumption of 20 times compared to the ARM7 processor, and
29 times compared to the TIC64x VLIW, when running the same benchmark capped
to the same throughput and for the same process technology (0.13渭m). When
compared to an equivalent RICA design, DRAP was up to 22% larger than RICA but
resulted in a power reduction of up to 1.9 times. It was also capable of achieving up
to 2.8 times higher throughputs than RICA for the same benchmarks
A Scalable and Adaptive Network on Chip for Many-Core Architectures
In this work, a scalable network on chip (NoC) for future many-core architectures is proposed and investigated. It supports different QoS mechanisms to ensure predictable communication. Self-optimization is introduced to adapt the energy footprint and the performance of the network to the communication requirements. A fault tolerance concept allows to deal with permanent errors. Moreover, a template-based automated evaluation and design methodology and a synthesis flow for NoCs is introduced
Specification and Verification of Pipelining in the ARM2 RISC Microprocessor
State Machines (ASMs) provide a sound mathematical basis for the specification and verification of systems. An application of the ASM methodology to the verification of a pipelined microprocessor (an ARM2 implementation) is described. Both the sequential execution model and final pipelined model are formalized using ASMs. A series of intermediate models are introduced that gradually expose the complications of pipelining. The first intermediate model is proven equivalent to the sequential model in the absence of structural, control, and data hazards. In the following steps, these simplifying assumptions are lifted one by one, and the original proof is refined to establish the equivalence of each intermediate model with the sequential model, leading ultimately to a full proof of equivalence of the sequential and pipelined models. Categories and Subject Descriptors: B.5.2 [Hardware]: Register transfer level implementation--- Design Aids; C.1.1 [Computer Systems Organization]: Processor ..