13,316 research outputs found

    On arbitrary-level IIR and FIR filters

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    A recently published method for designing IIR (infinite-impulse-response) digital filters with multilevel magnitude responses is reinterpreted from a different viewpoint. On the basis of this interpretation, techniques for extending these results to the case of finite-impulse-response (FIR) filters are developed. An advantage of the authors' method is that, when the arbitrary-level filter is implemented, its power-complementary filter, which may be required in specific applications, is obtained simultaneously. Also, by means of a tuning factor (a parameter of the scaling matrix), it is possible to generate a whole family of arbitrary-level filters

    Standard Transistor Array (STAR). Volume 1: Placement technique

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    A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties

    GRAPE-6: The massively-parallel special-purpose computer for astrophysical particle simulation

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    In this paper, we describe the architecture and performance of the GRAPE-6 system, a massively-parallel special-purpose computer for astrophysical NN-body simulations. GRAPE-6 is the successor of GRAPE-4, which was completed in 1995 and achieved the theoretical peak speed of 1.08 Tflops. As was the case with GRAPE-4, the primary application of GRAPE-6 is simulation of collisional systems, though it can be used for collisionless systems. The main differences between GRAPE-4 and GRAPE-6 are (a) The processor chip of GRAPE-6 integrates 6 force-calculation pipelines, compared to one pipeline of GRAPE-4 (which needed 3 clock cycles to calculate one interaction), (b) the clock speed is increased from 32 to 90 MHz, and (c) the total number of processor chips is increased from 1728 to 2048. These improvements resulted in the peak speed of 64 Tflops. We also discuss the design of the successor of GRAPE-6.Comment: Accepted for publication in PASJ, scheduled to appear in Vol. 55, No.

    Design, processing and testing of LSI arrays hybrid microelectronics task

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    Those factors affecting the cost of electronic subsystems utilizing LSI microcircuits were determined and the most efficient methods for low cost packaging of LSI devices as a function of density and reliability were developed

    Expansion of CMOS array design techniques

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    The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described

    Research in the effective implementation of guidance computers with large scale arrays Interim report

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    Functional logic character implementation in breadboard design of NASA modular compute

    Six-man, self-contained carbon dioxide concentrator subsystem for Space Station Prototype (SSP) application

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    A six man, self contained, electrochemical carbon dioxide concentrating subsystem for space station prototype use was successfully designed, fabricated, and tested. A test program was successfully completed which covered shakedown testing, design verification testing, and acceptance testing
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