A Downconversion Beamforming RF Front-End in 130 nm CMOS technology

Due to the exponential growth of wireless data communications an increasing number of components compete for space in the frequency spectrum. Nowadays, different approaches have been addressed in order to overcome this problem. One of these approaches is using spatial filters instead of time-domain ones. Since most wireless devices operate by transferring/receiving signals to/from all directions, interfering signals are becoming an increasing problem. Thus steering the transmission/reception of signals in a specific direction alleviates this problem, which is performed by employing multiple antennas. In the scope of the spatial filtering approach, a 1 GHz downconvertion 4-element phased array receiver front-end is presented in this thesis, implemented in 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The phase shifting of the beamforming receiver is implemented with a switched-capacitor vector modulator, that excels in its linearity and low power consumption. This receiver also provides a spatial rejection of more than 20 dB and good input matching

Advances in silicon phased-array receiver IC's

Phased-Arrays are increasingly used, and require Silicon implementations to result in affordable multi-beam systems. In this paper, CMOS implementations of two novel analogue beamforming multi-channel receivers will be presented. A narrow-band highly linear system exploiting switches and capacitors in advanced CMOS is presented, implementing a fully passive switched capacitor vector modulator exploiting a zero-IF I/Q mixer: This technique is not applicable to very wideband phased-array receivers. These systems require true-time delay beamforming, which is implemented in the second CMOS implementation. An innovative gm-RC implementation of a true-time delay cell is exploited in a four-channel beamforming receiver with more than L.5 GHz bandwidth, in a standard 0.13 um CMOS process. Professional phased-arrays can often not live with the dynamic range limitations imposed by these implementations. To that end a SiGe implementation of an integrated receiver was realized targeting a digital beamforming phased-array. Dynamic range and flexibility of use were the main driving factors. Alltogether, these results show large progress with respect to the feasibility of Silicon-based phased-array front-end implementation for commercial as well as professional phased-arrays. © 2012 IEEE

A 4-element phased-array system with simultaneous spatial- and frequency-domain filtering at the antenna inputs

To reject strong interference in excess of 0 dBm, a 4- element LO-phase shifting phased-array receiver with 8-phase passive mixers terminated by baseband capacitors is presented. The passive mixers upconvert both the spatial and frequency domain filtering from baseband to RF, hence realizing blocker suppression directly at the antenna inputs. A comprehensive mathematical model provides a set of closed-form equations describing the spatial and frequency domain filtering including imperfections. A prototype is realized in 28 nm CMOS. It exploits third harmonic reception to achieve a wide RF-frequency range from 0.6–4.5 GHz at 34–119 mW power dissipation, while also providing impedance matching. Out of the band/beam, a 1 dB-compression point as high as +12/+10 dBm has been measured. The 1-element noise figure over the RF-frequency range is 4–6.3 dB, while in-beam/band IIP3 values of 0– +2.6 dBm are measured. This proposed technique can be instrumental to make RF receivers more robust for interference, while still being flexibly tunable in frequency

Co-channel Blocker and Self-Interferer Tolerant Receiver Architectures for MIMO and Full-Duplex MIMO Receivers

This research focuses on receiver architectures which enable better spectral e�ciency by handling blockers in the same spectral range as the signal. The presence of such blockers, without the use of blocker cancelling/�ltering techniques leads to gain compression and hence, consequent performance degradation of receivers leading to reduced spectrum e�ciency. Two approaches have been devised, implemented in silicon and measured to demonstrate that they alleviate the problems associated with blockers. A system capable of handling co-channel spatially separated blockers is implemented in the �rst work and another system capable of handling self-interference caused due to the transmitter during full-duplex operation constitutes the second work. In the �rst work, a 4-channel phased array based on a novel architecture incorporating a coupler and a noise-cancelling LNA in combination with a polyphase �lter was implemented to eliminate spatial co-channel blockers. This approach allows signal reception from all directions except from the direction of the blocker providing better than 20dB blocker cancellation in the X-band. The second work is aimed at achieving true simultaneous transmit-and-receive (STAR) performance through a hybrid coupler based full-duplex integrated N-path based circulator-Rx architecture. STAR radios enable higher spectrum e�ciency and dynamic spectrum access. Integrating the shared antenna-interface is attractive for small-form factor and MIMO channel estimation. Implemented for frequencies ranging from 550MHz to 900MHz this work addresses the challenge of low-noise wideband self-interference-cancellation by demonstrating a wide band hybrid-coupler circulator antenna interface using N-path mixers that achieves low noise �gure while preserving the linearity of passive-mixer �rst receiver. Better than +5.5dBm power handling of self-interference while providing over 40dB average cancellation over a bandwidth of 56MHz with a 2.7dB noise �gure has been measured. Further, the full-duplex circulator architecture has been expanded to a MIMO implementation wherein we demonstrate a 65nm CMOS 2.2GHz 2x2 FD MIMO RX that achieves up to 35/45dB average self-interference-cancellation (SIC) across 40/20MHz BW with more than 42dB/53dB average cross-talk (CT)-SIC across 40/20MHz BW. Interference cancellation mechanisms cause < 2.1dB degradation in RX NF and allows an overall TX power handling of +14dBm enabled by clock bootstrapping

IF-Sampling Digital Beamforming with Bit-Stream Processing.

Beamforming in receivers improves signal-to-noise ratio (SNR), and enables spatial filtering of incoming signals, which helps reject interferers. However, power consump-tion, area, and routing complexity needed with an increasing number of elements have been a bottleneck to implementing efficient beamforming systems. Especially, digital beamforming (DBF), despite its versatility, has not been attractive for low-cost on-chip implementation due to its high power consumption and large die area for multiple high-performance analog-to-digital converters (ADCs) and an intensive digital signal process-ing (DSP) unit. This thesis presents a new DBF receiver architecture with direct intermediate frequency (IF) sampling. By adopting IF sampling in DBF, a digital-intensive beamforming receiver, which provides highly flexible and accurate beamforming, is achieved. The IF-sampling DBF receiver architecture is efficiently implemented with continuous-time band-pass delta-sigma modulators (CTBPDSMs) and bit-stream processing (BSP). They have been separately investigated, and have not been considered for DBF until now. The unique combination of CTBPDSMs and BSP enables low-power and area-efficient DBF by removing the need for digital multipliers and multiple decimators. Two prototype digital beamformers (prototype I and prototype II) are fabricated in 65 nm complementary metal-oxide-semiconductor (CMOS) technology. The prototype I forms a single beam from four 265 MHz IF inputs, and an array signal-to-noise-plus-distortion ratio (SNDR) of 56.6 dB is achieved over a 10 MHz bandwidth. The prototype I consumes 67.2 mW, and occupies 0.16 mm2. The prototype II forms two simultaneous beams from eight 260 MHz IF inputs, and an array SNDR of 63.3 dB is achieved over a 10 MHz bandwidth. The prototype II consumes 123.7 mW, and occupies 0.28 mm2. The two prototypes are the first on-chip implementation of IF-sampling DBF.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/116778/1/jaehun_1.pd

Scalable Array Transceivers with Wide Frequency Tuning Range for Next Generation Radios

Scalable array transceivers with wide frequency tuning range are attractive for next-generationradios. Key challenges for such radios include generation of LO signals with widefrequency tuning range, scalable synchronization between multiple array unit cells andtolerance to in-band and out-of-band interferers. This thesis presents approaches toaddress these challenges in commercial CMOS technologies.The first part focuses on a series resonant mode-switching VCO architecture thatachieves both state-of-art area and power efficiency with an octave frequency tuningrange from 6.4-14 GHz achieved 186-dB-188-dB Figure-of-Merit (FoM) in 65 nm CMOStechnology. The scalability of this approach towards achieving even larger FTR is alsodemonstrated by a triple-mode 2.2 GHz to 8.7 GHz (119% FTR) CMOS VCO.In the second part a scalable, single-wire coupled-PLL architecture for RF mm-wavearrays is presented. The proposed architecture preserves the simplicity of a daisy-chained LO distribution, compensates for phase offset due to interconnect, and provides phasenoise improvement commensurate to the number of coupled PLLs. Measurements on a28 GHz CMOS prototype demonstrate the feasibility of this scheme.The third part of this thesis presents filtering techniques for in-band blocker suppression.A spatial spectral notch filter design for MIMO digital beam forming arrays is proposedto relax the ADC dynamic range requirement. Orthogonal properties of Walsh functionsincorporated into passive N-path approach enables reconfigurable notches at multiplefrequencies and angles-of-incidence. A 0.3 GHz-1.4 GHz four-element array prototypeimplemented in 65 nm CMOS achieves > 15-dB notch filtering at RF input for twoblockers while causing < 3-dB NF degradation.Finally, a code-domain N-path receiver (RX) is proposed based on pseudo-random(PN) code-modulated LO pulses for simultaneous transmission and reception (STAR)applications. A combination of Walsh-Function and PN sequence is proposed to createcode-domain matched filter at the RF frontend which reflects unknown in-band blockersand rejects known in-band TX self-interference (SI) by using orthogonal codes at RXinput thereby maximizing the SNR of the received signals. The resulting prototype in65 nm is functional from 0.3 GHz-1.4 GHz with 35 dB gain and concurrently receivestwo code-modulated signals. Proposed transmitter (TX) SI mitigation approach resultsin 38.5 dB rejection for -11.8 dBm 1.46 Mb s QPSK modulated SI at RX input. TheRX achieves 23.7 dBm OP1dB for in-band SI, while consuming ∼35 mW and occupies0.31 mm2Keywords: Passive Mixers, dual band, TX self-Interferer, synchronisation, STAR, Code domain N-path receiver, mode switching, notch filter, Phase locked loops, Octave tuning range, CMOS, phase noise, VCO, large-scale 5G mm-wave arrays, resonator, Simultaneous transmit and receive, resonator band-switching, LO distribution, scalable coupled-PLL, N-path passive mixers, MIMO arrays, digital beamforming, CDMA, phased arrays, wide tuning range, Walsh Functio

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

Circuit Design Techniques For Wideband Phased Arrays

University of Minnesota Ph.D. dissertation.June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xii, 143 pages.This dissertation focuses on beam steering in wideband phased arrays and phase noise modeling in injection locked oscillators. Two different solutions, one in frequency and one in time, have been proposed to minimize beam squinting in phased arrays. Additionally, a differential current reuse frequency doubler for area and power savings has been proposed. Silicon measurement results are provided for the frequency domain solution (IBM 65nm RF CMOS), injection locked oscillator model verification (IBM 130nm RF-CMOS) and frequency doubler (IBM 65nm RF CMOS), while post extraction simulation results are provided for the time domain phased array solution (the chip is currently under fabrication, TSMC 65nm RF CMOS). In the frequency domain solution, a 4-point passive analog FFT based frequency tunable filter is used to channelize an incoming wideband signal into multiple narrowband signals, which are then processed through independent phase shifters. A two channel prototype has been developed at 8GHz RF frequency. Three discrete phase shifts (0 & +/- 90 degrees) are implemented through differential I-Q swapping with appropriate polarity. A minimum null-depth of 19dB while a maximum null-depth of 27dB is measured. In the time domain solution, a discrete time approach is undertaken with signals getting sampled in order of their arrival times. A two-channel prototype for a 2GHz instantaneous RF bandwidth (7GHz-9GHz) has been designed. A QVCO generates quadrature LO signals at 8GHz which are phase shifted through a 5-bit (2 extra bits from differential I-Q swapping with appropriate polarity) cartesian combiner. Baseband sampling clocks are generated from phase shifted LOs through a CMOS divide by 4 with independent resets. The design achieves an average time delay of 4.53ps with 31.5mW of power consumption (per channel, buffers excluded). An injection locked oscillator has been analyzed in s-domain using Paciorek's time domain transient equations. The simplified analysis leads to a phase noise model identical to that of a type-I PLL. The model is equally applicable to injection locked dividers and multipliers and has been extended to cover all injection locking scenarios. The model has been verified against a discrete 57MHz Colpitt's ILO, a 6.5GHz ILFD and a 24GHz ILFM with excellent matching between the model and measurements. Additionally, a differential current reuse frequency doubler, for frequency outputs between 7GHz to 14GHz, design has been developed to reduce passive area and dc power dissipation. A 3-bit capacitive tuning along with a tail current source is used to better conversion efficiency. The doubler shows FOM$_{T}$ values between 191dBc/Hz to 209dBc/Hz when driven by a 0.7GHz to 5.8GHz wide tuning VCO with a phase noise that ranges from -114dBc/Hz to -112dBc/Hz over the same bandwidth

Circuit Techniques for Multiple and Wideband Beamforming

University of Minnesota Ph.D. dissertation.June 2018. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); x, 102 pages.This thesis presents different architectures with regard to multiple beamforming and wideband phased array transceiver. Three different designs are implemented in TSMC 65nm RF CMOS to demonstrate different solutions. The design in this thesis have included major RF blocks in state-of-art wireless transceiver: RF receiver, local oscillator, and RF transmitter. First, a RF/analog FFT based four-channel four-beam receiver with progressive partial spatial ltering is proposed. This architecture is particularly well suited for MIMO systems where multiple beams are used to increase throughput. Like the FFT, the proposed architecture reuses computations for multi-beam systems. In particular, the proposed architecture redistributes the computations so as to maximize the reuse of the structure that already exist in a receiver chain. In many fashions the architecture is quite similar to a Butler matrix but unlike the Butler matrix it does not use large passive components at RF. Further, we exploit the normally occurring quadrature down-conversion process to implement the tap weights. In comparison to traditional MIMO architectures, that effectively duplicate each path, the distributed computations of this architecture provide partial spatial ltering before the final stage, improving interference rejection for the blocks between the LNA and the ADC. Additionally, because of the spatial ltering prior to the ADC, a single interferer only jams a single beam allowing for continued operation though at a lower combined throughput. The four-beam receiver core prototype in 65nm CMOS implements the basic FFT based architecture but does not include an LNA or extensive IF stages. This four-channel design consumes 56mW power and occupies an active area of 0:65mm2 excluding pads and test circuits. Second, a wideband phased array receiver architecture with simultaneous spectral and spatial filtering by sub-harmonic injection oscillators is presented. The design avoids using expensive delay elements by many conventional wideband phased array. Different from prior art of channelization which cannot solve beam-squinting issue among the sub-channels, we use sub-harmonic injection locking scheme, which make the center frequencies of all sub-channels point to the same spatial direction to overcome beam-squinting issue. The low frequency, low power and narrowband phase shifters are placed at LO in comparison to conventional way of placing delay elements or phase shifters in the signal path. This avoids receiver performance degradation from delay elements or phase shifters. The simultaneous spectral and spatial ltering dictates less ADC dynamic range requirement and further reduces power. The injection locking scheme reduces the phase noise contribution from the oscillators. The two-band prototype design realized in 65nm GP CMOS is centered at 9GHz, provides 4GHz instantaneous bandwidth, reduces beam-squinting by half, consumes 31.75mW/antenna and occupies 2.7mm2 of chip area. In the third work, a steerable RF/analog FFT based four-beam transmitter architecture is presented. This work is based on the idea of FFT based multiple beamforming in 1st work, but extended to the transmitter and make the all beams steerable. Due to the reciprocity between receiver and transmitter, decimation-in-frequency (DIF) FFT is utilized in the transmitter. All the beams are steered simultaneously by front-end phase shifters, while keep each of the beams is independent of the others. The steerability of FFT based multiple beamforming scheme makes this proposed prototype could tackle more complicated portable wireless environment. The first and second proposed architecture have been silicon veried, and the design of the third has been finished and ready for tapeout

Sistemas eficientes de transmissão de energia sem-fios e identificação por radiofrequência

Doutoramento em Engenharia EletrotécnicaIn the IoT context, where billions of connected objects are expected to be ubiquitously deployed worldwide, the frequent battery maintenance of ubiquitous wireless nodes is undesirable or even impossible. In these scenarios, passive-backscatter radios will certainly play a crucial role due to their low cost, low complexity and battery-free operation. However, as passive-backscatter devices are chiefly limited by the WPT link, its efficiency optimization has been a major research concern over the years, gaining even more emphasis in the IoT context. Wireless power transfer has traditionally been carried out using CW signals, and the efficiency improvement has commonly been achieved through circuit design optimization. This thesis explores a fundamentally different approach, in which the optimization is focused on the powering waveforms, rather than the circuits. It is demonstrated through theoretical analysis, simulations and measurements that, given their greater ability to overcome the built-in voltage of rectifying devices, high PAPR multi-sine (MS) signals are capable of more efficiently exciting energy harvesting circuits when compared to CWs. By using optimal MS signals to excite rectifying devices, remarkable RF-DC conversion efficiency gains of up to 15 dB with respect to CW signals were obtained. In order to show the effectiveness of this approach to improve the communication range of passive-backscatter systems, a MS front-end was integrated in a commercial RFID reader and a significant range extension of 25% was observed. Furthermore, a software-defined radio RFID reader, compliant with ISO18000-6C standard and with MS capability, was constructed from scratch. By interrogating passive RFID transponders with MS waveforms, a transponder sensitivity improvement higher than 3 dB was obtained for optimal MS signals. Since the amplification and transmission of high PAPR signals is critical, this work also proposes efficient MS transmitting architectures based on space power combining techniques. This thesis also addresses other not less important issues, namely self-jamming in passive RFID readers, which is the second limiting factor of passive-backscatter systems. A suitable self-jamming suppression scheme was first used for CW signals and then extended to MS signals, yielding a CW isolation up to 50 dB and a MS isolation up 60 dB. Finally, a battery-less remote control system was developed and integrated in a commercial TV device with the purpose of demonstrating a practical application of wireless power transfer and passive-backscatter concepts. This allowed battery-free control of four basic functionalities of the TV (CH+,CH-,VOL+,VOL-).No contexto da internet das coisas (IoT), onde são esperados bilhões de objetos conectados espalhados pelo planeta de forma ubíqua, torna-se impraticável uma frequente manutenção e troca de baterias dos dispositivos sem fios ubíquos. Nestes cenários, os sistemas radio backscatter passivos terão um papel preponderante dado o seu baixo custo, baixa complexidade e não necessidade de baterias nos nós móveis. Uma vez que a transmissão de energia sem fios é o principal aspeto limitativo nestes sistemas, a sua otimização tem sido um tema central de investigação, ganhando ainda mais ênfase no contexto IoT. Tradicionalmente, a transferência de energia sem-fios é feita através de sinais CW e a maximização da eficiência é conseguida através da otimização dos circuitos recetores. Neste trabalho explora-se uma abordagem fundamentalmente diferente, em que a otimização foca-se nas formas de onda em vez dos circuitos. Demonstra-se, teoricamente e através de simulações e medidas que, devido à sua maior capacidade em superar a barreira de potencial intrínseca dos dispositivos retificadores, os sinais multi-seno (MS) de elevado PAPR são capazes de excitar os circuitos de colheita de energia de forma mais eficiente quando comparados com o sinal CW tradicional. Usando sinais MS ótimos em circuitos retificadores, foram verificadas experimentalmente melhorias de eficiência de conversão RF-DC notáveis de até 15 dB relativamente ao sinal CW. A fim de mostrar a eficácia desta abordagem na melhoria da distância de comunicação de sistemas backscatter passivos, integrou-se um front-end MS num leitor RFID comercial e observou-se um aumento significativo de 25% na distância de leitura. Além disso, desenvolveu-se de raiz um leitor RFID baseado em software rádio, compatível com o protocolo ISO18000-6C e capaz de gerar sinais MS, com os quais interrogou-se transponders passivos, obtendo-se ganhos de sensibilidade dos transponders maiores que 3 dB. Uma vez que a amplificação de sinais de elevado PAPR é uma operação crítica, propôs-se também novas arquiteturas eficientes de transmissão baseadas na combinação de sinais em espaço livre. Esta tese aborda também outros aspetos não menos importantes, como o self-jamming em leitores RFID passivos, tido como o segundo fator limitativo neste tipo de sistemas. Estudou-se técnicas de cancelamento de self-jamming CW e estendeu-se o conceito a sinais MS, tendo-se obtido isolamentos entre o transmissor e o recetor de até 50 dB no primeiro caso e de até 60 dB no segundo. Finalmente, com o objetivo de demonstrar uma aplicação prática dos conceitos de transmissão de energia sem fios e comunicação backscatter, desenvolveu-se um sistema de controlo remoto sem pilhas, cujo protótipo foi integrado num televisor comercial a fim de controlar quatro funcionalidades básicas (CH+,CH-,VOL+,VOL-)