Secure Key Encapsulation Mechanism with Compact Ciphertext and Public Key from Generalized Srivastava code

Code-based public key cryptosystems have been found to be an interesting option in the area of Post-Quantum Cryptography. In this work, we present a key encapsulation mechanism (KEM) using a parity check matrix of the Generalized Srivastava code as the public key matrix. Generalized Srivastava codes are privileged with the decoding technique of Alternant codes as they belong to the family of Alternant codes. We exploit the dyadic structure of the parity check matrix to reduce the storage of the public key. Our encapsulation leads to a shorter ciphertext as compared to DAGS proposed by Banegas et al. in Journal of Mathematical Cryptology which also uses Generalized Srivastava code. Our KEM provides IND-CCA security in the random oracle model. Also, our scheme can be shown to achieve post-quantum security in the quantum random oracle model

Spinal codes

Spinal codes are a new class of rateless codes that enable wireless networks to cope with time-varying channel conditions in a natural way, without requiring any explicit bit rate selection. The key idea in the code is the sequential application of a pseudo-random hash function to the message bits to produce a sequence of coded symbols for transmission. This encoding ensures that two input messages that differ in even one bit lead to very different coded sequences after the point at which they differ, providing good resilience to noise and bit errors. To decode spinal codes, this paper develops an approximate maximum-likelihood decoder, called the bubble decoder, which runs in time polynomial in the message size and achieves the Shannon capacity over both additive white Gaussian noise (AWGN) and binary symmetric channel (BSC) models. Experimental results obtained from a software implementation of a linear-time decoder show that spinal codes achieve higher throughput than fixed-rate LDPC codes, rateless Raptor codes, and the layered rateless coding approach of Strider, across a range of channel conditions and message sizes. An early hardware prototype that can decode at 10 Mbits/s in FPGA demonstrates that spinal codes are a practical construction.Massachusetts Institute of Technology (Irwin and Joan Jacobs Presidential Fellowship)Massachusetts Institute of Technology (Claude E. Shannon Assistantship)Intel Corporation (Intel Fellowship

Algebraic Codes For Error Correction In Digital Communication Systems

Access to the full-text thesis is no longer available at the author's request, due to 3rd party copyright restrictions. Access removed on 29.11.2016 by CS (TIS).Metadata merged with duplicate record (http://hdl.handle.net/10026.1/899) on 20.12.2016 by CS (TIS).C. Shannon presented theoretical conditions under which communication was possible error-free in the presence of noise. Subsequently the notion of using error correcting codes to mitigate the effects of noise in digital transmission was introduced by R. Hamming. Algebraic codes, codes described using powerful tools from algebra took to the fore early on in the search for good error correcting codes. Many classes of algebraic codes now exist and are known to have the best properties of any known classes of codes. An error correcting code can be described by three of its most important properties length, dimension and minimum distance. Given codes with the same length and dimension, one with the largest minimum distance will provide better error correction. As a result the research focuses on finding improved codes with better minimum distances than any known codes. Algebraic geometry codes are obtained from curves. They are a culmination of years of research into algebraic codes and generalise most known algebraic codes. Additionally they have exceptional distance properties as their lengths become arbitrarily large. Algebraic geometry codes are studied in great detail with special attention given to their construction and decoding. The practical performance of these codes is evaluated and compared with previously known codes in different communication channels. Furthermore many new codes that have better minimum distance to the best known codes with the same length and dimension are presented from a generalised construction of algebraic geometry codes. Goppa codes are also an important class of algebraic codes. A construction of binary extended Goppa codes is generalised to codes with nonbinary alphabets and as a result many new codes are found. This construction is shown as an efficient way to extend another well known class of algebraic codes, BCH codes. A generic method of shortening codes whilst increasing the minimum distance is generalised. An analysis of this method reveals a close relationship with methods of extending codes. Some new codes from Goppa codes are found by exploiting this relationship. Finally an extension method for BCH codes is presented and this method is shown be as good as a well known method of extension in certain cases

Expander Graphs and Coding Theory

Expander graphs are highly connected sparse graphs which lie at the interface of many different fields of study. For example, they play important roles in prime sieves, cryptography, compressive sensing, metric embedding, and coding theory to name a few. This thesis focuses on the connections between sparse graphs and coding theory. It is a major challenge to explicitly construct sparse graphs with good expansion properties, for example Ramanujan graphs. Nevertheless, explicit constructions do exist, and in this thesis, we survey many of these constructions up to this point including a new construction which slightly improves on an earlier edge expansion bound. The edge expansion of a graph is crucial in applications, and it is well-known that computing the edge expansion of an arbitrary graph is NP-hard. We present a simple algo-rithm for approximating the edge expansion of a graph using linear programming techniques. While Andersen and Lang (2008) proved similar results, our analysis attacks the problem from a different vantage point and was discovered independently. The main contribution in the thesis is a new result in fast decoding for expander codes. Current algorithms in the literature can decode a constant fraction of errors in linear time but require that the underlying graphs have vertex expansion at least 1/2. We present a fast decoding algorithm that can decode a constant fraction of errors in linear time given any vertex expansion (even if it is much smaller than 1/2) by using a stronger local code, and the fraction of errors corrected almost doubles that of Viderman (2013)

Spinal codes

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from PDF student-submitted version of thesis.Includes bibliographical references (p. 52-55).Spinal codes are a new class of rateless codes that enable wireless networks to cope with time-varying channel conditions in a natural way, without requiring any explicit bit rate selection. The key idea in the code is the sequential application of a pseudo-random hash function to the message bits, to produce a sequence of coded symbols for transmission. This encoding ensures that two input messages that differ in even one bit lead to very different coded sequences after the point at which they differ, providing good resilience to noise and bit errors. To decode spinal codes, we develop an approximate maximum-likelihood decoder, called the bubble decoder, which runs in time polynomial in the message size and achieves the Shannon capacity over both additive white Gaussian noise (AWGN) and binary symmetric channel (BSC) models. The decoder trades off throughput for computation (hardware area or decoding time), allowing the decoder to scale gracefully with available hardware resources. Experimental results obtained from a software implementation of a linear-time decoder show that spinal codes achieve higher throughput than fixed-rate LDPC codes [11], rateless Raptor codes [35], and the layered rateless coding approach [8] of Strider [12], across a wide range of channel conditions and message sizes. An early hardware prototype that can decode at 10 Mbits/s in FPGA demonstrates that spinal codes are a practical construction.by Jonathan Perry.S.M

Anticodes and error-correcting for digital data transmission

The work reported in this thesis is an investigation in the field of error-control coding. This subject is concerned with increasing the reliability of digital data transmission through a noisy medium, by coding the transmitted data. In this respect, an extension and development of a method for finding optimum and near-optimum codes, using N.m digital arrays known as anticodes, is established and described. The anticodes, which have opposite properties to their complementary related error-control codes, are disjoined fron the original maximal-length code, known as the parent anticode, to leave good linear block codes. The mathematical analysis of the parent anticode and as a result the mathematical analysis of its related anticodes has given some useful insight into the construction of a large number of optimum and near-optimum anticodes resulting respectively in a large number of optimum and near-optimum codes. This work has been devoted to the construction of anticodes from unit basic (small dimension) anticodes by means of various systematic construction and refinement techniques, which simplifies the construction of the associated linear block codes over a wide range of parameters. An extensive list of these anticodes and codes is given in the thesis. The work also has been extended to the construction of anticodes in which the symbols have been chosen from the elements of the finite field GF(q), and, in particular, a large number of optimum and near-optimum codes over GF(3) have been found. This generalises the concept of anticodes into the subject of multilevel codes

Direct Antenna Modulation using Frequency Selective Surfaces

In the coming years, the number of connected wireless devices will increase dramatically, expanding the Internet of Things (IoT). It is likely that much of this capacity will come from network densification. However, base stations are inefficient and expensive, particularly the downlink transmitters. The main cause of this is the power amplifier (PA), which must amplify complex signals, so are expensive and often only 30% efficient. As such, the cost of densifying cellular networks is high. This thesis aims to overcome this problem through codesign of a low complexity, energy efficient transmitter through electromagnetic design; and a waveform which leverages the advantages and mitigates the disadvantages of the new technology, while being suitable for supporting IoT devices. Direct Antenna Modulation (DAM) is a low complexity transmitter architecture, where modulation occurs at the antenna at transmit power. This means a non-linear PA can efficiently amplify the carrier wave without added distortion. Frequency Selective Surfaces (FSS) are presented here as potential phase modulators for DAM transmitters. The theory of operation is discussed, and a prototype DAM for QPSK modulation is simulated, designed and tested. Next, the design process for a continuous phase modulating antenna is explored. Simulations and measurement are used to fully characterise a prototype, and it is implemented in a line-of-sight end-to-end communications system, demonstrating BPSK, QPSK and 8-PSK. Due to the favourable effects of spread spectrum signalling on FSS DAM performance, Cyclic Prefix Direct Sequence Spread Spectrum (CPDSSS) is developed. Conventional spreading techniques are extended using a cyclic prefix, making multipath interference entirely defined by the periodic autocorrelation of the sequence used. This is demonstrated analytically, through simulation and with experiments. Finally, CPDSSS is implemented using FSS DAM, demonstrating the potential of this new low cost, low complexity transmitter with CPDSSS as a scalable solution to IoT connectivity