On board processor system study Final report

Development and characteristics of onboard processor syste

A model of a generalized chip structure

Three distinct levels can be distinguished in the design of digital systems: architecture, implementation and realization. Description methods are available at each level assuming that at the realization level components such as nands and nors are used. The introduction of programmable components, such as microprocessors and programmable input/output chips, which now form the basis elements at the realization level, forces to reconsider these description methods

Graphical microcode simulator with a reconfigurable datapath

Microcode is a symbolic way to simplify control design that allows changing, testing and updating the control unit of processors. By changing the microcode, the same datapath can be used for an entirely different application, such as supporting a completely different instruction set. For these reasons, a majority of control units in modern day processors are microcoded. The object was to investigate and implement a graphical microcode simulator with a reconfigurable datapath and microcode format. By allowing a wide configuration of the datapath, many types of logical processors can be designed and simulated. The resulting implemented simulator is able to fill the void in microprogramming tools since there are no graphical microcode simulators that allow such customization of the datapath. The customization of the datapath goes beyond allowing different files specifying the datapath, it allows the datapath to be created and modified using the graphical interface.This tool is able to be used to design and simulate general-purpose processors and application specific processors through datapath and microcode configurations. In the academic setting, this tool provides easier microcode testing through verification on the instruction level for instructors and provide simulation debugging through code tracing and breakpoints for students

Graph model analysis of computer structures

Graph theory is applicable to the solving of problems in nearly every field of scientific study. The purpose of this thesis is to consider its applications in representing and analyzing digital computers. Fundamental graph theory definitions, the types and the properties of the directed graphs, the matrix representation, and several reduction techniques are discussed. The blocking gate method for diagnosing computer systems is described and applied to the Scientific Control Corporation (SCC) 650 for its fault-diagnosis. Microprogramming has been a significant trend in hardware and software designs of computers. Microprogrammed computers are discussed in comparison to conventional computers. A general scheme utilizing four nodes generates directed graphs for both types of architecture. The directed graphs are studied with respect to the flexibility and cost parameters --Abstract, page ii

Wepsim: an online interactive educational simulator integrating microdesign, microprogramming, and assembly language programming

Our educational project has three primary goals. First, we want to provide a robust vision of how hardware and software interplay, by integrating the design of an instruction set (through microprogramming) and using that instruction set for assembly programming. Second, we wish to offer a versatile and interactive tool where the previous integrated vision could be tested. The tool we have developed to achieve this is called WepSIM and it provides the view of an elemental processor together with a microprogrammed subset of the MIPS instruction set. In addition, WepSIM is flexible enough to be adapted to other instruction sets or hardware components (e.g., ARM or x86). Third, we want to extend the activities of our university courses, labs, and lectures (fixed hours in a fixed place), so that students may learn by using their mobile device at any location, and at any time during the day. This article presents how WepSIM has improved the teaching of Computer Structure courses by empowering students with a more dynamic and guided learning process. In this paper, we show the results obtained during the experience of using the simulator in the Computer Structure course of the Bachelor's Degree in Computer Science and Engineering at University Carlos III of Madrid

Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities

Date of Conference: 20-22 Nov. 2019; Conference Location: Bilbao, Spain[Abstract] The problem of generating complex synchronization patterns using automated tools is addressed in this paper. This work was originally motivated by the need of fast and jitter free synchronization in scientific facilities, where a large number of sensors and actuators must be controlled at the right time in a variety of situations. Programmable processors cannot meet the real-time requirements, forcing to use dedicated circuits to produce and transmit the control signals. Designing application specific hardware by hand is a slow and error-prone task. Hence, a set of tools is required that allow specifying the control systems in a clear and efficient way and producing synthesizable HDL (hardware description language) code in an automated manner. Statechart diagrams have been selected as the input method, and this work focuses on how to translate those diagrams into HDL code. We present a tool that analyzes a Statecharts specification and implements the required control systems using FPGAs. A number of solutions are provided to deal with multiple triggering events and concurrent super-states. Also, an alternative microprogrammed implementation is proposed.This work was funded in part by the Ministry of Economy and Competitiveness of Spain, Project TIN2016-75845-P (AEI/FEDER, UE), Xunta de Galicia and FEDER funds of the EU under the Consolidation Program of Competitive Reference Groups (ED431C 2017/04), and under the Centro Singular de Investigaci ´on de Galicia accreditation 2016-2019 (ED431G/01)Xunta de Galicia; ED431C 2017/04Xunta de Galicia; ED431G/0

The location of innovative activity in Europe

In this paper we use new data to describe how firms from 15 European countries organise their innovative activities. The data matches firm level accounting data with information on the patents that those firms and their subsidiaries have applied for at the European Patents Office. We describe the data in detail