2,161 research outputs found
SAT-Based Synthesis Methods for Safety Specs
Automatic synthesis of hardware components from declarative specifications is
an ambitious endeavor in computer aided design. Existing synthesis algorithms
are often implemented with Binary Decision Diagrams (BDDs), inheriting their
scalability limitations. Instead of BDDs, we propose several new methods to
synthesize finite-state systems from safety specifications using decision
procedures for the satisfiability of quantified and unquantified Boolean
formulas (SAT-, QBF- and EPR-solvers). The presented approaches are based on
computational learning, templates, or reduction to first-order logic. We also
present an efficient parallelization, and optimizations to utilize reachability
information and incremental solving. Finally, we compare all methods in an
extensive case study. Our new methods outperform BDDs and other existing work
on some classes of benchmarks, and our parallelization achieves a super-linear
speedup. This is an extended version of [5], featuring an additional appendix.Comment: Extended version of a paper at VMCAI'1
New developments in the theory of Groebner bases and applications to formal verification
We present foundational work on standard bases over rings and on Boolean
Groebner bases in the framework of Boolean functions. The research was
motivated by our collaboration with electrical engineers and computer
scientists on problems arising from formal verification of digital circuits. In
fact, algebraic modelling of formal verification problems is developed on the
word-level as well as on the bit-level. The word-level model leads to Groebner
basis in the polynomial ring over Z/2n while the bit-level model leads to
Boolean Groebner bases. In addition to the theoretical foundations of both
approaches, the algorithms have been implemented. Using these implementations
we show that special data structures and the exploitation of symmetries make
Groebner bases competitive to state-of-the-art tools from formal verification
but having the advantage of being systematic and more flexible.Comment: 44 pages, 8 figures, submitted to the Special Issue of the Journal of
Pure and Applied Algebr
Skolem Functions for Factored Formulas
Given a propositional formula F(x,y), a Skolem function for x is a function
\Psi(y), such that substituting \Psi(y) for x in F gives a formula semantically
equivalent to \exists F. Automatically generating Skolem functions is of
significant interest in several applications including certified QBF solving,
finding strategies of players in games, synthesising circuits and bit-vector
programs from specifications, disjunctive decomposition of sequential circuits
etc. In many such applications, F is given as a conjunction of factors, each of
which depends on a small subset of variables. Existing algorithms for Skolem
function generation ignore any such factored form and treat F as a monolithic
function. This presents scalability hurdles in medium to large problem
instances. In this paper, we argue that exploiting the factored form of F can
give significant performance improvements in practice when computing Skolem
functions. We present a new CEGAR style algorithm for generating Skolem
functions from factored propositional formulas. In contrast to earlier work,
our algorithm neither requires a proof of QBF satisfiability nor uses
composition of monolithic conjunctions of factors. We show experimentally that
our algorithm generates smaller Skolem functions and outperforms
state-of-the-art approaches on several large benchmarks.Comment: Full version of FMCAD 2015 conference publicatio
A Multi-Core Solver for Parity Games
We describe a parallel algorithm for solving parity games,\ud
with applications in, e.g., modal mu-calculus model\ud
checking with arbitrary alternations, and (branching) bisimulation\ud
checking. The algorithm is based on Jurdzinski's Small Progress\ud
Measures. Actually, this is a class of algorithms, depending on\ud
a selection heuristics.\ud
\ud
Our algorithm operates lock-free, and mostly wait-free (except for\ud
infrequent termination detection), and thus allows maximum\ud
parallelism. Additionally, we conserve memory by avoiding storage\ud
of predecessor edges for the parity graph through strictly\ud
forward-looking heuristics.\ud
\ud
We evaluate our multi-core implementation's behaviour on parity games\ud
obtained from mu-calculus model checking problems for a set of\ud
communication protocols, randomly generated problem instances, and\ud
parametric problem instances from the literature.\ud
\u
Sciduction: Combining Induction, Deduction, and Structure for Verification and Synthesis
Even with impressive advances in automated formal methods, certain problems
in system verification and synthesis remain challenging. Examples include the
verification of quantitative properties of software involving constraints on
timing and energy consumption, and the automatic synthesis of systems from
specifications. The major challenges include environment modeling,
incompleteness in specifications, and the complexity of underlying decision
problems.
This position paper proposes sciduction, an approach to tackle these
challenges by integrating inductive inference, deductive reasoning, and
structure hypotheses. Deductive reasoning, which leads from general rules or
concepts to conclusions about specific problem instances, includes techniques
such as logical inference and constraint solving. Inductive inference, which
generalizes from specific instances to yield a concept, includes algorithmic
learning from examples. Structure hypotheses are used to define the class of
artifacts, such as invariants or program fragments, generated during
verification or synthesis. Sciduction constrains inductive and deductive
reasoning using structure hypotheses, and actively combines inductive and
deductive reasoning: for instance, deductive techniques generate examples for
learning, and inductive reasoning is used to guide the deductive engines.
We illustrate this approach with three applications: (i) timing analysis of
software; (ii) synthesis of loop-free programs, and (iii) controller synthesis
for hybrid systems. Some future applications are also discussed
SAT-Solving in Practice, with a Tutorial Example from Supervisory Control
Satisfiability solving, the problem of deciding whether the variables of a propositional formula can be assigned in such a way that the formula evaluates to true, is one of the classic problems in computer science. It is of theoretical interest because it is the canonical NP-complete problem. It is of practical interest because modern SAT-solvers can be used to solve many important and practical problems. In this tutorial paper, we show briefly how such SAT-solvers are implemented, and point to some typical applications of them. Our aim is to provide sufficient information (much of it through the reference list) to kick-start researchers from new fields wishing to apply SAT-solvers to their problems. Supervisory control theory originated within the control community and is a framework for reasoning about a plant to be controlled and a specification that the closed-loop system must fulfil. This paper aims to bridge the gap between the computer science community and the control community by illustrating how SAT-based techniques can be used to solve some supervisory control related problems
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