Development of convective reflow-projection moire warpage measurement system and prediction of solder bump reliability on board assemblies affected by warpage

Out-of-plane displacement (warpage) is one of the major thermomechanical reliability concerns for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may cause serious reliability problems. In this research, a convective reflow and projection moire warpage measurement system was developed. The system is the first real-time, non-contact, and full-field measurement system capable of measuring PWB/PWBA/chip package warpage with the projection moire technique during different thermal reflow processes. In order to accurately simulate the reflow process and to achieve the ideal heating rate, a convective heating system was designed and integrated with the projection moire system. An advanced feedback controller was implemented to obtain the optimum heating responses. The developed system has the advantages of simulating different types of reflow processes, and reducing the temperature gradients through the PWBA thickness to ensure that the projection moire system can provide more accurate measurements. Automatic package detection and segmentation algorithms were developed for the projection moire system. The algorithms are used for automatic segmentation of the PWB and assembled packages so that the warpage of the PWB and chip packages can be determined individually. The effect of initial PWB warpage on the fatigue reliability of solder bumps on board assemblies was investigated using finite element modeling (FEM) and the projection moire system. The 3-D models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different chip packages mounted on PWBs. The simulation results were validated and correlated with the experimental results obtained using the projection moire system and accelerated thermal cycling tests. Design of experiments and an advanced prediction model were generated to predict solder bump fatigue life based on the initial PWB warpage, package dimensions and locations, and solder bump materials. This study led to a better understanding of the correlation between PWB warpage and solder bump thermomechanical reliability on board assemblies.Ph.D.Committee Chair: Dr. Ume, I. Charles; Committee Member: Dr. Book, Wayne; Committee Member: Dr. Kim, Yeong; Committee Member: Dr. Pan, Jiahui; Committee Member: Dr. Sitaraman, Suresh; Committee Member: Dr. Wu, C. F. Jef

Design of Experiment Analysis of an Electronics Package Lid Using Finite Element Analysis

A design of experiment analysis is reported on data from warpage simulations using finite element analysis of a lidded electronics package. Warpage in a lid of an optical electronics package can detrimentally affect the reliability of the package as well as its optical performance. The present study focuses on the variety of materials and designs of lids relevant to recent technologies in electronics packaging. The finite element analysis (FEA) formulation in this study accurately predicts deformation and warpage in the elastic region with optimal computational time achieved through a choice of boundary conditions and mesh sensitivity studies. The results from FEA are compared to analytical calculations made using the classical laminate plate theory (CLPT) as well as the modified Suhir’s theory. It is observed that FEA results are more accurate as they account for the performance of die attach/ underfill materials regardless of the small thickness of the layer. The FEA data are finally used to conduct a design of experiments (DOE) analysis to investigate the influence of 3 distinct designs and 6 material choices on warpage of a lid. The analysis indicates that there is no significant interaction between the two parameters expected to affect the warpage in the lid. Material properties of the lid are found to have a greater effect on the warpage of the lid as compared to variabilities introduced in lid designs in this study. The FEA simulations performed consider only material behavior within the elastic limit and, in some situations, plastic deformation may occur which is more permanent and as such requires a more comprehensive analysis in the plastic region to enhance the data set for DOE studies

Digital fringe projection system for measuring warpage of painted and unpainted PBGAs and boards and FEA studies of PBGA warpage

Improvements in chip package technologies have led to smaller package sizes and higher density circuitry that require superior reliability of chip packages. One of the crucial factors affecting the reliability of chip packages is warpage which primarily occurs during the reflow process. Because warpage may cause serious reliability problems such as solder bump failure and die cracking, warpage control has become a crucial task. Advancements in warpage measurement and prediction would provide important steps toward addressing this concern. Among the various warpage measurement techniques, fringe projection techniques (i.e., laser fringe projection (LFP) and digital fringe projection (DFP)) have emerged as recent trends due to their non-contact, full-field, and high-resolution (for small viewing area) capabilities for measuring the warpage of chip packages and boards (i.e., printed wiring boards (PWBs) and PWB assemblies). In this research, the measurement capabilities of a LFP system were improved by reducing its laser speckle noise and post-processing time, and a novel DFP system for measuring the warpage of painted and unpainted chip packages and boards was developed. Also, parametric studies were performed to predict the warpage of plastic ball grid array packages affected by four geometric factors. Finally, a guideline that manufacturing engineers can use for selecting the most suitable warpage measurement technique for their particular application was developed. The results of this study will help to improve the yields and reliability of chip packages and boards, reduce the manufacturing costs and time to market for chip packages and boards and ultimately reduce the prices of end-products.Ph.D

Numerical analysis of lead-free solder joints: effects of thermal cycling and electromigration

To meet the requirements of miniaturization and multifunction in microelectronics, understanding of their reliability and performance has become an important research subject in order to characterise electronics served under various loadings. Along with the demands of the increasing miniaturization of electronic devices, various properties and the relevant thermo-mechanical-electrical response of the lead-free solder joints to thermal cycling and electro-migration become the critical factors, which affect the service life of microelectronics in different applications. However, due to the size and structure of solder interconnects in microelectronics, traditional methods based on experiments are not applicable in the evaluation of their reliability under complex joint loadings. This thesis presents an investigation, which is based on finite-element method, into the performance of lead-free solder interconnects under thermal fatigue and electro-migration, specifically in the areas as follows: (1) the investigation of thermal-mechanical performance and fatigue-life prediction of flip-chip package under different sizes to achieve a further understanding of IMC layer and size effects of a flip chip package under thermal cycling; (2) the establishment of a numerical method, simulating void-formation/crack-propagation based on the results of finite-element analysis, to allow the prediction of crack evolution and failure time for electro-migration reliability of solder bumps; (3) the establishment of a flow-based algorithm for combination effects of thermal-mechanical and electro-migration that was subsequent implemented in to an FE model to evaluate the reliability assessment of service lives associated with a flip chip package

ADVANCED SHADOW MOIRE WITH NON-CONVENTIONAL IMAGING ANGLES

With the increasingly smaller electronic package size, warpage of electronic packages becomes an important measurement related to the reliability of the products. Higher sensitivity out-of-plane deformation techniques are required to capture the smaller deformations of tiny packages for enhanced design analysis and model verification. The higher sensitivity is realized using non-zero viewing angles with the conventional shadow moiré technique. Advanced configurations to accommodate the non-zero viewing angles are developed to cope with direct reflection encountered on the conventional setup. An expanded governing equation for the configuration is derived and verified experimentally. Then the proposed configuration was implemented in the testing of an actual package to demonstrate the advantages that accrue from the higher sensitivity

Evaluation of solder-joint reliability for a 10mm Quad Flat Leadless package with top-side paddle using classical models for a leadless device and accelerated life testing

The standard QFN package consists of a leadless perimeter array and a bottom solderable thermal paddle. The thermal performance of the package can be improved by moving the paddle to the topside. The soldered surface area of the package reduces by about 80% with a top-side paddle. The soldered-joint life will also reduce due to the significant thermal coefficient of expansion mismatch between the QFN package and the circuit board. The solder-joint reliability of a large QFN package with top-side paddle is not well understood. This thesis evaluates the solder-joint reliability of a 10mm square leadless QFN package with top-side paddle. The analysis includes several classical models for a leadless package and compares modeling results to accelerated reliability testing. The accelerated tests include the influence mold compound and lead finish play on solder-joint life and ways to improve solder-joint reliability

Développement de procédés avancés d'encapsulation de composants microélectroniques basés sur les techniques de thermocompression

L'un des grands défis de la recherche et développement est d'optimiser l'ensemble du cycle de fabrication d'un produit microélectronique, depuis sa conception jusqu’à sa tenue mécanique en service. Un objectif essentiel des entreprises était de réduire le temps de cycles d’assemblage afin de minimiser les coûts de production. La phase d’assemblage des composants microélectroniques est l'une des étapes clé qui doit être bien optimisée afin d’atteindre l’objectif de minimisation du temps de cycle. La méthode d'assemblage traditionnelle des puces par refusion (en anglais mass reflow MR) convenait généralement à une fabrication à grand volume, en particulier pour des puces à pas standard d'environ 150 μm. Cependant, la forte demande du marché pour des interconnexions à pas plus fin, pour permettre un nombre d'entrée/sortie (Input/Output : I/O) plus élevé dans un facteur de forme plus petit, a entraîné une transition du processus de la liaison MR conventionnel à l'assemblage par thermocompression (en anglais ThermoCompression Bonding TCB). Bien que le procédé TCB offre un assemblage de plus grande précision et permet l'utilisation des pas d'interconnexion plus fins, il présente également de nouveaux défis. L'un des problèmes majeurs de l'assemblage TCB est qu'il s'agit d'un processus assez long, dans lequel chaque puce doit être passée indépendamment à travers un cycle TCB complet, incluant le chauffage, le maintien de la température et le refroidissement. Cela entraîne une diminution significative de la productivité par rapport au MR. Le débit de production peut être amélioré en réduisant le temps nécessaire pour atteindre les températures de processus requises. Cependant, des variations thermiques peuvent se produire aux interfaces de liaison, entraînant une mauvaise uniformité de température sur la surface de la puce et conduisant à des régions où le point de fusion de la brasure n'est pas atteint. Ainsi, il est extrêmement important de prévoir et contrôler la température réelle à l'interface de liaison afin d’obtenir une bonne uniformité thermique et des joints de brasure sans défaut. C'est dans cette perspective que s'inscrit les travaux menés dans la première partie de la thèse. Le premier objectif de cette étude était donc de déterminer la durée minimum de temps de chauffe nécessaire assurant une uniformité de température optimal et par conséquent des joints de brasure de bonne qualité. Pour atteindre cet objectif, il fallait alors proposer et valider une nouvelle méthodologie pour estimer la température d'interface lors d'un processus TCB. Une évaluation de l'influence de différentes vitesses de chauffe sur la distribution de température à travers la surface de la puce, ainsi que sur la qualité de liaison résultante, a été réalisée à l’aide d’un capteur de type RTD (). Les résultats ont montré que les défauts de brasure observés aux interfaces de liaison peuvent éventuellement être liés à une mauvaise uniformité de température, liée à des vitesses de chauffe élevées. Des variations thermiques acceptables ont été trouvées à une faible vitesse de chauffage de 80°C/s. Par conséquent, pour surmonter les températures de processus élevées et leurs effets néfastes sur la productivité, le développement d'une nouvelle méthode d’assemblage TCB à basse température devient primordiale. Le développement d’une nouvelle méthode de liaison par thermocompression à l'état solide détecteur de température résistif, Resistance Temperature Detector en anglais était donc notre second objectif dans cette étude. Cette méthode est basée sur la création d'une liaison mécanique temporaire initiale au début du processus de packaging (en utilisant une pression à une température inférieure au point de fusion de la brasure). Les joints de iv brasure seront entièrement refondus à la fin du processus de packaging, lorsque les billes de brasure BGA (ball-grid-array) seront brasées au substrat. Cette nouvelle méthode peut surmonter les limitations associées au processus TCB conventionnel, notamment la température élevée, le processus d'assemblage lent et les contraintes mécaniques élevées. Une investigation a été menée pour déterminer les conditions d'assemblage appropriées à appliquer pendant ce processus. Des investigations supplémentaires ont été également menées pour explorer le mécanisme d'assemblage responsable de l’assemblage mécanique temporaire. Les résultats préliminaires de cette méthode sont prometteurs, montrant des joints de brasure de bonne qualité formés en un temps d'assemblage très court (6 secondes) et à des températures bien inférieures au TCB conventionnel (200°C)

Modeling the SAC microstructure evolution under thermal, thermomechanical and electrical constraints

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PCB Quality Metrics that Drive Reliability (PD 18)

Risk based technology infusion is a deliberate and systematic process which defines the analysis and communication methodology by which new technology is applied and integrated into existing and new designs, identifies technology development needs based on trends analysis and facilitates the identification of shortfalls against performance objectives. This presentation at IPC Works Asia Aerospace 2019 Events provides the audience a snapshot of quality variations in printed wiring board quality, as assessed, using experiences in processing and risk analysis of PWB structural integrity coupons. The presentation will focus on printed wiring board quality metrics used, the relative type and number of non-conformances observed and trend analysis using statistical methods. Trend analysis shows the top five non-conformances observed across PWB suppliers, the root cause(s) behind these non-conformance and suggestions of mitigation plans. The trends will then be matched with the current state of the PWB supplier base and its challenges and opportunities. The presentation further discusses the risk based SMA approaches and methods being applied at GSFC for evaluating candidate printed wiring board technologies which promote the adoption of higher throughput and faster processing technology for GSFC missions

Lifetime modelling of large area solder joints in power electronic inverter units

Power electronics (PE) modules in inverter units are a critical part of the Hybrid/Electric vehicles drivetrain. During passive temperature cycling, the solder joint between the PE module and the baseplate develops cracks. A detailed reliability investigation was carried out on multiple physical variants under three temperature cycling profiles to uncover major influence parameters. A stress triaxiality and inelastic strain based FEM damage parameter was formulated which showed excellent correlation with experimental results.Leistungselektronikmodule (PE) in Wechselrichtern sind ein wichtiger Bestandteil von Hybrid-/Elektrofahrzeugen. Bei passivem Temperaturwechsel entwickelt die Lötstelle zwischen dem PE-Modul und der Grundplatte Risse. Es wurde eine detaillierte Zuverlässigkeitsuntersuchung an mehreren physikalischen Varianten unter drei Temperaturwechselprofile durchgeführt, um die wichtigsten Einflussparameter aufzudecken. Es wurde ein auf Spannungs-Triaxialität und unelastischer Dehnung basierender FEM-Schadensparameter formuliert, der eine ausgezeichnete Korrelation mit experimentellen Ergebnissen zeigte