Volumetric Display Research

The goal of this project was to research and develop a volumetric display system that allows a three-dimensional CAD file to be displayed in real space. The system used a Xilinx Zynq SoC to process a CAD model into a series of two-dimensional images to be projected onto a spinning helicoid surface using DLP technology. The SoC contained a combination of custom logic on FPGA fabric as well as software on an embedded processor to implement the unique system functionality

Automatic transmit power control for power efficient communications in UAS

Nowadays, unmanned aerial vehicles (UAV) have become one of the most popular tools that can be used in commercial, scientific, agricultural and military applications. As drones become faster, smaller and cheaper, with the ability to add payloads, the usage of the drone can be versatile. In most of the cases, unmanned aerials systems (UAS) are equipped with a wireless communication system to establish a link with the ground control station to transfer the control commands, video stream, and payload data. However, with the limited onboard calculation resources in the UAS, and the growing size and volume of the payload data, computational complex signal processing such as deep learning cannot be easily done on the drone. Hence, in many drone applications, the UAS is just a tool for capturing and storing data, and then the data is post-processed off-line in a more powerful computing device. The other solution is to stream payload data to the ground control station (GCS) and let the powerful computer on the ground station to handle these data in real-time. With the development of communication techniques such as orthogonal frequency-division multiplexing (OFDM) and multiple-input multiple-output (MIMO) transmissions, it is possible to increase the spectral efficiency over large bandwidths and consequently achieve high transmission rates. However, the drone and the communication system are usually being designed separately, which means that regardless of the situation of the drone, the communication system is working independently to provide the data link. Consequently, by taking into account the position of the drone, the communication system has some room to optimize the link budget efficiency. In this master thesis, a power-efficient wireless communication downlink for UAS has been designed. It is achieved by developing an automatic transmit power control system and a custom OFDM communication system. The work has been divided into three parts: research of the drone communication system, an optimized communication system design and finally, FPGA implementation. In the first part, an overview on commercial drone communication schemes is presented and discussed. The advantages and disadvantages shown are the source of inspiration for improvement. With these ideas, an optimized scheme is presented. In the second part, an automatic transmit power control system for UAV wireless communication and a power-efficient OFDM downlink scheme are proposed. The automatic transmit power control system can estimate the required power level by the relative position between the drone and the GCS and then inform the system to adjust the power amplifier (PA) gain and power supply settings. To obtain high power efficiency for different output power levels, a searching strategy has been applied to the PA testbed to find out the best voltage supply and gain configurations. Besides, the OFDM signal generation developed in Python can encode data bytes to the baseband signal for testing purpose. Digital predistortion (DPD) linearization has been included in the transmitter’s design to guarantee the signal linearity. In the third part, two core algorithms: IFFT and LUT-based DPD, have been implemented in the FPGA platform to meet the real-time and high-speed I/O requirements. By using the high-level synthesis design process provided by Xilinx Corp, the algorithms are implemented as reusable IP blocks. The conclusion of the project is given in the end, including the summary of the proposed drone communication system and envisioning possible future lines of research

PWM controller design with Zynq SoC

The project is the development of a digital pulse-width modulation controller using Zynq technology, a system-on-chip that integrates a processor and programmable logic components. This technology enables offloading data processing to the hardware, to obtain the parallelization and acceleration of the control system to achieve a faster response. It also allows the creation of specific subsystems for tasks such as data flow, event synchronization, and management of input and output commands. The system can control up to two variable of a process through a dual mode control loop, which is implemented using a combination of software and hardware. The software can execute a configuration program and then run a high-level control algorithm that can be potentially complex. On the other hand, the programmable logic is pre-configured using a hardware description language that the compiler translates for the specific technology employed. By doing so, the project is flexible because both the hardware and software can be reprogrammed according to the requirements. These requirements can vary in nature, including increased performance, compatibility with interfacing devices, or the need to isolate subsystems for function verification. Finally, it was possible to verify the system and its components at each development stage, both internally using integrated logic analyzers and with the hardware-in-the-loop methodology.The project is the development of a digital pulse-width modulation controller using Zynq technology, a system-on-chip that integrates a processor and programmable logic components. This technology enables offloading data processing to the hardware, to obtain the parallelization and acceleration of the control system to achieve a faster response. It also allows the creation of specific subsystems for tasks such as data flow, event synchronization, and management of input and output commands. The system can control up to two variable of a process through a dual mode control loop, which is implemented using a combination of software and hardware. The software can execute a configuration program and then run a high-level control algorithm that can be potentially complex. On the other hand, the programmable logic is pre-configured using a hardware description language that the compiler translates for the specific technology employed. By doing so, the project is flexible because both the hardware and software can be reprogrammed according to the requirements. These requirements can vary in nature, including increased performance, compatibility with interfacing devices, or the need to isolate subsystems for function verification. Finally, it was possible to verify the system and its components at each development stage, both internally using integrated logic analyzers and with the hardware-in-the-loop methodology

FPGA-based multi-view stereo system with flexible measurement setup

In recent years, stereoscopic image processing algorithms have gained importance for a variety of applications. To capture larger measurement volumes, multiple stereo systems are combined into a multi-view stereo (MVS) system. To reduce the amount of data and the data rate, calculation steps close to the sensors are outsourced to Field Programmable Gate Arrays (FPGAs) as upstream computing units. The calculation steps include lens distortion correction, rectification and stereo matching. In this paper a FPGA-based MVS system with flexible camera arrangement and partly overlapping field of view is presented. The system consists of four FPGA-based passive stereoscopic systems (Xilinx Zynq-7000 7020 SoC, EV76C570 CMOS sensor) and a downstream processing unit (Zynq Ultrascale ZU9EG SoC). This synchronizes the sensor near processing modules and receives the disparity maps with corresponding left camera image via HDMI. The subsequent computing unit calculates a coherent 3D point cloud. Our developed FPGA-based 3D measurement system captures a large measurement volume at 24 fps by combining a multiple view with eight cameras (using Semi-Global Matching for an image size of 640 px × 460 px, up to 256 px disparity range and with aggregated costs over 4 directions). The capabilities and limitation of the system are shown by an application example with optical non-cooperative surface

Design and Development of an FPGA-based Medical EIS System

Electrical impedance spectroscopy is a powerful technique which can be used to characterize properties of many materials, including biological tissues. In medical applications, it is typically used as a complementary tool for diagnostic, helping improve the ability of current techniques to distinguish pathological tissue from normal tissue. Commercially available equipment to perform impedance measurements is usually expensive and impractical, lacking the necessary flexibility and compactness to use it as a fast prototype tool for research. The high cost and the difficulty in transporting it make it unsuitable for early-stage investigation in real-world clinical settings. Consequently, researchers at the Electronic and Biomedical Instrumentation Group at the Universitat Politècnica de Catalunya have been working on low-cost alternatives, which try to solve the aforementioned issues. The system described in this work aims to be such an alternative, being based on a low-cost electronic board capable of performing fast signal generation and data acquisition. In particular, its main focus is on fast measurements using multisine signals, with the one employed in this work consisting of 26 frequency components from 1 kHz to 1 MHz. The system has been designed with flexibility in mind, allowing the user to have complete control over the generation and acquisition chains thanks to its highly modular architecture, making it particularly well-suited for research purposes. The objective of this document is to give a thorough overview of the design and implementation of this system, focusing on the main architectural ideas but also covering many of the finer details. Some measurements, performed at a rate of approximately 950 spectrums per second, are briefly discussed at the end, and they serve both as validation of the implemented design and as an outline for future research directions

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms

FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel characterizers are the main considered applications that can benefit from the high processing rate, power efficiency and flexibility of FPGAs. Furthermore, the implementations of encryption/decryption algorithms by employing the Xilinx Zynq Ultrascale+MPSoC ZCU102 FPGA platform are discussed, and then we introduce our high-speed and lightweight implementation of the well-known AES-128 algorithm, developed on the same FPGA platform, and comparing it with similar solutions already published in the literature. The comparison results indicate that our AES-128 implementation enables efficient hardware usage for a given data-rate (up to 28.16 Gbit/s), resulting in higher efficiency (8.64 Mbps/slice) than other considered solutions. Finally, the applications of the ZCU102 platform for high-speed processing are explored, such as image and signal processing, visual recognition, and hardware resource management

A compact high-energy particle detector for low-cost deep space missions

Over the last few decades particle physics has led to many new discoveries, laying the foundation for modern science. However, there are still many unanswered questions which the next generation of particle detectors could address, potentially expanding our knowledge and understanding of the Universe. Owing to recent technological advancements, electronic sensors are now able to acquire measurements previously unobtainable, creating opportunities for new deep-space high-energy particle missions. Consequently, a new compact instrument was developed capable of detecting gamma rays, neutrons and charged particles. This instrument combines the latest in FPGA System-on-Chip technology as the central processor and a 3x3 array of silicon photomultipliers coupled with an organic plastic scintillator as the detector. Using modern digital pulse shape discrimination and signal processing techniques, the scintillator and photomultiplier combination has been shown to accurately discriminate between the di_erent particle types and provide information such as total energy and incident direction. The instrument demonstrated the ability to capture 30,000 particle events per second across 9 channels - around 15 times that of the U.S. based CLAS detector. Furthermore, the input signals are simultaneously sampled at a maximum rate of 5 GSPS across all channels with 14-bit resolution. Future developments will include FPGA-implemented digital signal processing as well as hardware design for small satellite based deep-space missions that can overcome radiation vulnerability