Satisfying hard real-time constraints using COTS components

L'utilizzo di componenti COTS (Commercial-Off-The-Shelf) è sempre più comune nella produzione di sistemi embedded real-time. Prodotti commerciali, come periferiche di Input/Output e bus di sistema, vengono utilizzati in sistemi real-time al fine di ridurre i costi, il tempo di produzione, ed aumentare le performance. Sfortunatamente, hardware e sistemi operativi COTS sono progettati principalmente per ottimizzare le performance, ma con poca attenzione verso determinismo, predicibilità ed affidabilità. Per questa ragione, molte problematiche devono ancora essere affrontate prima di un loro impiego in sistemi real-time ad alta criticita'. In questa tesi abbiamo centrato la nostra attenzione su alcune delle piu' importanti sorgenti di impredicibilita' che devono essere rimosse al fine di integrare hardware e software COTS in sistemi hard real-time. Come prima cosa abbiamo sviluppato ASMP-Linux, una variante di Linux che minimizza overhead e latenza del sistema operativo. Successivamente abbiamo progettato ed implementato un nuovo sistema di gestione dell'I/O, basato sul Real-Time Bridge, un nuovo componente hardware che fornisce isolamento temporale sui bus COTS e rimuove le interferenze fra periferiche di I/O. E' stato anche sviluppato un Multi-Flow Real-Time Bridge per assicurare predicibilita' nel caso di periferiche condivise. Infine abbiamo proposto PREM, un nuovo modello di esecuzione per sistemi real-time che elimina le interferenze fra periferiche e CPU, e quelle fra processi ad alta criticita' ed interruzioni hardware. Per ognuna delle nostre soluzioni saranno descritti in dettaglio gli aspetti teorici, l'implementazione dei prototipi ed i risultati sperimentali.Real-time embedded systems are increasingly being built using Commercial Off-The-Shelf (COTS) components such as mass-produced peripherals and buses to reduce costs, time-to-market, and increase performance. Unfortunately, COTS hardware and operating systems are typically designed to optimize average performance, instead of determinism, predictability, and reliability, hence their employment in high criticality real-time systems is still a daunting task. In this thesis, we addressed some of the most important sources of unpredictability which must be removed in order to integrate COTS hardware and software into hard real-time systems. We first developed ASMP-Linux, a variant of Linux, capable of minimizing both operating system overhead and latency. Next, we designed and implemented a new I/O management system, based on real-time bridges, a novel hardware component that provides temporal isolation on the COTS bus and removes the interference among I/O peripherals. A multi-flow real-time bridge has been also developed to address interperipheral interference, allowing predictable device sharing. Finally, we propose PREM, a new execution model for real-time systems which eliminates interference between peripherals and the CPU, as well as interference between a critical task and driver interrupts. For each of our solutions, we will describe in detail theory aspects, as well as prototype implementations and experimental measurements

Scratchpad Memory Management For Multicore Real-Time Embedded Systems

Multicore systems will continue to spread in the domain of real-time embedded systems due to the increasing need for high-performance applications. This research discusses some of the challenges associated with employing multicore systems for safety-critical real-time applications. Mainly, this work is concerned with providing: 1) efficient inter-core timing isolation for independent tasks, and 2) predictable task communication for communicating tasks. Principally, we introduce a new task execution model, based on the 3-phase execution model, that exploits the Direct Memory Access (DMA) controllers available in modern embedded platforms along with ScratchPad Memories (SPMs) to enforce strong timing isolation between tasks. The DMA and the SPMs are explicitly managed to pre-load tasks from main memory into the local (private) scratchpad memories. Tasks are then executed from the local SPMs without accessing main memory. This model allows CPU execution to be overlapped with DMA loading/unloading operations from and to main memory. We show that by co-scheduling task execution on CPUs and using DMA to access memory and I/O, we can efficiently hide access latency to physical resources. In turn, this leads to significant improvements in system schedulability, compared to both the case of unregulated contention for access to physical resources and to previous cache and SPM management techniques for real-time systems. The presented SPM-centric scheduling algorithms and analyses cover single-core, partitioned, and global real-time systems. The proposed scheme is also extended to support large tasks that do not fit entirely into the local SPM. Moreover, the schedulability analysis considers the case of recovering from transient soft errors (bit flips caused by a single event upset) in several levels of memories, that cannot be automatically corrected in hardware by the ECC unit. The proposed SPM-centric scheduling is integrated at the OS level; thus it is transparent to applications. The proposed scheme is implemented and evaluated on an FPGA platform and a Commercial-Off-The-Shelf (COTS) platform. In regards to real-time task communication, two types of communication are considered. 1) Asynchronous inter-task communication, between either sequential tasks (single-threaded) or parallel tasks (multi-threaded). 2) Intra-task communication, where parallel threads of the same application exchange data. A new task scheduling model for parallel tasks (Bundled Scheduling) is proposed to facilitate intra-task communication and reduce synchronization overheads. We show that the proposed bundled scheduling model can be applied to several parallel programming models, such as fork-join and DAG-based applications, leading to improved system schedulability. Finally, intra-task communication is governed by a predictable inter-core communication platform. Specifically, we propose HopliteRT, a lean and predictable Network-on-Chip that connects the private SPMs