Exploring Microfluidic Design Automation: Thin-wall Membrane Regulator

Microfluidics and lab-on-a-chip are a growing technology, influential in many areas of engineering. This project focuses on the necessity for better computer aided design tools for this area. Specifically, it focuses on the automated synthesis of T-junction components with thin-walled membranes for stability. A T-junction is a passive droplet generation component, common in microfluidics which suffers from behavior instability in highly integrated circuits with many components. One way of improving stability is using flexible membranes to mitigate pressure perturbations. This thesis describes the design process of such membranes so that a model can be used to synthesize stable T-junctions. The thesis also discusses Manifold, a software framework for automated synthesis of microfluidic circuits. This is the framework where the design process fits in. To compare the result of the software framework with the analytic model described, physical circuits were fabricated to validate the accuracy of the analytic model and the software. Besides the T-junction, another microfluidics component that was investigated was a “Capillary Electrophoresis Channel”. This component was also investigated with respect to automated synthesis and verification using the Manifold framework, and the details are discussed

Genuine lab experiences for students in resource constrained environments: The RealLab with integrated intelligent assessment.

Laboratory activities are indispensable for developing engineering skills. Computer Aided Learning (CAL) tools can be used to enhance laboratory learning in various ways, the latest approach being the virtual laboratory technique that emulates traditional laboratory processes. This new approach makes it possible to give students complete and genuine laboratory experiences in situations constrained by limited resources in the provision of laboratory facilities and infrastructure and/or where there is need for laboratory education, for large classes, with only one laboratory stand. This may especially be the case in countries in transition. Most existing virtual laboratories are not available for purchase. Where they are, they may not be cost friendly for resource constrained environments. Also, most do not integrate any form of assessment structure. In this paper, we present a very cost friendly virtual laboratory solution for genuine laboratory experiences in resource constrained environments, with integrated intelligent assessment

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

LOT: Logic Optimization with Testability - new transformations for logic synthesis

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

Innovative teaching of IC design and manufacture using the Superchip platform

In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime

NASA Thesaurus Supplement: A three part cumulative supplement to the 1982 edition of the NASA Thesaurus (supplement 2)

The three part cumulative NASA Thesaurus Supplement to the 1982 edition of the NASA Thesaurus includes: part 1, hierarchical listing; part 2, access vocabulary, and part 3, deletions. The semiannual supplement gives complete hierarchies for new terms and includes new term indications for terms new to this supplement