Real-time adaptive filtering of dental drill noise using a digital signal processor

The application of noise reduction methods requires the integration of acoustics engineering and digital signal processing, which is well served by a mechatronic approach as described in this paper. The Normalised Least Mean Square (NLMS) algorithm is implemented on the Texas Instruments TMS320C6713 DSK Digital Signal Processor (DSP) as an adaptive digital filter for dental drill noise. Blocks within the Matlab/Simulink Signal Processing Blockset and the Embedded Target for TI C6000 DSP family are used. A working model of the algorithm is then transferred to the Code Composer Studio (CCS), where the desired code can be linked and transferred to the target DSP. The experimental rig comprises a noise reference microphone, a microphone for the desired signal, the DSK and loudspeakers. Different load situations of the dental drill are considered as the noise characteristics change when the drill load changes. The result is that annoying drill noise peaks, which occur in a frequency range from 1.5 kHz to 10 kHz, are filtered out adaptively by the DSP. Additionally a schematic design for its implementation in a dentist’s surgery will also be presented

VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems

The rapid evolution of wireless access is creating an ever changing variety of standards for indoor and outdoor environments. The real-time processing demands of wireless data rates in excess of 100 Mbps is a challenging problem for architecture design and verification. In this paper, we consider current trends in VLSI architecture and in rapid prototyping testbeds to evaluate these systems. The key phases in multi-standard system design and prototyping include: Algorithm Mapping to Parallel Architectures – based on the real-time data and sampling rate and the resulting area, time and power complexity; Configurable Mappings and Design Exploration – based on heterogeneous architectures consisting of DSP, programmable application-specific instruction (ASIP) processors, and co-processors; and Verification and Testbed Integration – based on prototype implementation on programmable devices and integration with RF units.Nokia Foundation FellowshipNokia CorporationNational InstrumentsNational Science Foundatio

Dynamic Capacity Enhancement using a Smart Antenna in Mobile Telecommunications Networks

This work describes an investigation into the performance of antennas for mobile base station applications and techniques for improving the coverage and capacity within a base station cell. The work starts by tracing the development of mobile systems, both in technical and commercial terms, from the earliest analogue systems to present day broadband systems and includes anticipated future developments. This is followed by an outline of how smart antenna systems can be utilised to improve cell coverage and capacity. A novel smart antenna system incorporating an array of slant ± 450 dual- polarised stacked patch elements four columns wide excited by a novel multi-beam forming and beam shaping network has been designed, simulated and implemented. It is found that for an ideal smart antenna array, four narrow overlapping beams, one wide “broadcast channel” beam and right and left shaped beams can be provided. Results are presented for the simulation of the smart antenna system using CST EM simulation software which inherently includes mutual coupling and the effects of a truncated ground plane on the element patterns. The results show some significant changes to the desired set of coverage patterns and various mutual coupling compensation techniques have been reviewed. An improved design technique has been developed for compensating the performance degrading effects of mutual coupling and finite ground plane dimensions in microstrip antenna arrays. The improved technique utilises combination of two previously known techniques: complex excitation weights compensation by inversion of the array mutual coupling scattering matrix and the incorporation of a WAIM (wide angle impedance matching) sheet. The technique has been applied to a novel multi-beam smart antenna array to demonstrate the efficacy of the technique by electromagnetic simulation. In addition, a demonstrator array has been constructed and tested which has yielded a positive conformation of the simulation results. For the developed demonstrator array which provides seven different beams, beams “footprints” have been predicted both for free space propagation and for urban propagation to evaluate the dynamic capacity performance of the smart antenna in a 3G mobile network. The results indicate that sector capacity can be dynamically tailored to user demand profiles by selection of the appropriate beam patterns provided by the novel smart antenna system

Datacenter Design for Future Cloud Radio Access Network.

Cloud radio access network (C-RAN), an emerging cloud service that combines the traditional radio access network (RAN) with cloud computing technology, has been proposed as a solution to handle the growing energy consumption and cost of the traditional RAN. Through aggregating baseband units (BBUs) in a centralized cloud datacenter, C-RAN reduces energy and cost, and improves wireless throughput and quality of service. However, designing a datacenter for C-RAN has not yet been studied. In this dissertation, I investigate how a datacenter for C-RAN BBUs should be built on commodity servers. I first design WiBench, an open-source benchmark suite containing the key signal processing kernels of many mainstream wireless protocols, and study its characteristics. The characterization study shows that there is abundant data level parallelism (DLP) and thread level parallelism (TLP). Based on this result, I then develop high performance software implementations of C-RAN BBU kernels in C++ and CUDA for both CPUs and GPUs. In addition, I generalize the GPU parallelization techniques of the Turbo decoder to the trellis algorithms, an important family of algorithms that are widely used in data compression and channel coding. Then I evaluate the performance of commodity CPU servers and GPU servers. The study shows that the datacenter with GPU servers can meet the LTE standard throughput with 4× to 16× fewer machines than with CPU servers. A further energy and cost analysis show that GPU servers can save on average 13× more energy and 6× more cost. Thus, I propose the C-RAN datacenter be built using GPUs as a server platform. Next I study resource management techniques to handle the temporal and spatial traffic imbalance in a C-RAN datacenter. I propose a “hill-climbing” power management that combines powering-off GPUs and DVFS to match the temporal C-RAN traffic pattern. Under a practical traffic model, this technique saves 40% of the BBU energy in a GPU-based C-RAN datacenter. For spatial traffic imbalance, I propose three workload distribution techniques to improve load balance and throughput. Among all three techniques, pipelining packets has the most throughput improvement at 10% and 16% for balanced and unbalanced loads, respectively.PhDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/120825/1/qizheng_1.pd

Market impact of SR

Thesis (S.M.)--Massachusetts Institute of Technology, Engineering Systems Division, Technology and Policy Program, 2002.Includes bibliographical references (p. 163-169).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Software radio (SR) is a new technology where signal-processing software running over general-purpose hardware platforms performs the radio functions. This approach promises to solve the issues that traditional radios face today, enhance competitiveness and accelerate the development of wireless communications. Lots of expectations have been put on SR. Nevertheless, SR is a still developing technology whose capabilities and implications have not been deeply studied. This thesis puts some clarity on the impact of SR through four steps: first, considering the technical constraints of SR and how they may affect its evolution; second, evaluating the SR benefits assuming that there are neither regulatory nor economic hurdles; third, analyzing the impact of SR on the stakeholders; and fourth, discussing the current regulatory framework and proposing changes to reduce barriers to SR development. This thesis finds that SR capabilities may be applied to multiple commercial sectors. A/D converters and semiconductors capacity limit the full implementation of these scenarios. Battery life is a further problem for SR devices. SR disrupts the traditional wireless value chain: general-purpose processors will capture market share from dedicated semiconductors; traditional radio manufacturers will compete against general-purpose platforms vendors, operating system designers and software programmers. Such changes modify the upper layers. In the cellular industry, SR reduces deployment costs in at least 33% per standard and operation costs in at least 47% per standard, promotes VMNOs, modifies the business model of players like site owners and improves roaming. In the short-term, FCC certification rules may damage SR development and adoption. In the long-term, software radio might provide the means to relax the need for standardization and improve spectrum management policies.by Maria Fuencisla Merino Artalejo.S.M

FPGA Hardware Implementation of DOA Estimation Algorithm Employing LU Decomposition

In this paper, authors present their work on field-programmable gate array (FPGA) hardware implementation of proposed direction of arrival estimation algorithms employing LU factorization. Both L and U matrices were considered in computing the angle estimates. Hardware implementation was done on a Virtex-5 FPGA and its experimental verification was performed using National Instruments PXI platform which provides hardware modules for data acquisition, RF down-conversion, digitization, etc. A uniform linear array consisting of four antenna elements was deployed at the receiver. LabVIEW FPGA modules with high throughput math functions were used for implementing the proposed algorithms. MATLAB simulations of the proposed algorithms were also performed to validate the efficacy of the proposed algorithms prior to hardware implementation of the same. Both MATLAB simulation and experimental verification establish the superiority of the proposed methods over existing methods reported in the literature, such as QR decomposition-based implementations. FPGA compilation results report low resource usage and faster computation time compared with the QR-based hardware implementation. Performance comparison in terms of estimation accuracy, percentage resource utilization, and processing time is also presented for different data and matrix sizes