A software service supporting software quality forecasting

Software repositories such as source control, defect tracking systems and project management tools, are used to support the progress of software projects. The exploitation of such data with techniques like forecasting is becoming an increasing need in several domains to support decision-making processes. However, although there exist several statistical tools and languages supporting forecasting, there is a lack of friendly approaches that enable practitioners to exploit the advantages of creating and using such models in their dashboard tools. Therefore, we have developed a modular and flexible forecasting service allowing the interconnection with different kinds of databases/data repositories for creating and exploiting forecasting models based on methods like ARIMA or ETS. The service is open source software, has been developed in Java and R and exposes its functionalities through a REST API. Architecture details are provided, along with functionalities’ description and an example of its use for software quality forecasting.Peer ReviewedPostprint (author's final draft

An orchestrator for dynamic interconnection of software components

Composing and orchestrating software components is a fundamental concern in modern software engineering. This paper addresses the possibility of such orchestration being dynamic, in the sense that the structure of component's interconnection patterns can change at run-time. The envisaged approach extends previous work by the authors on the use of coalgebraic models for the specification of software connectors.POSI/ICHS/44304/200

Using ER Models for Microprocessor Functional Test Coverage Evaluation

Test coverage evaluation is one of the most critical issues in microprocessor software-based testing. Whenever the test is developed in the absence of a structural model of the microprocessor, the evaluation of the final test coverage may become a major issue. In this paper, we present a microprocessor modeling technique based on entity-relationship diagrams allowing the definition and the computation of custom coverage functions. The proposed model is very flexible and particularly effective when a structural model of the microprocessor is not availabl

Directory Based Cache Coherency Protocols for Shared Memory Multiprocessors

Directory based cache coherency protocols can be used to build large scale, weakly ordered, shared memory multiprocessors. The salient feature of these protocols is that they are interconnection network independent, making them more scaleable than snoopy bus protocols. The major criticisms of previously defined directory protocols point to the size of memory heeded to store the directory and the amount of communication across the interconnection network required to maintain coherence. This thesis tries solving these problems by changing the entry format of the global table, altering the architecture of the global table, and developing new protocols. Some alternative directory entry formats are described, including a special entry format for implementing queueing semaphores. Evaluation of the various entry formats is done with probabilistic models of shared cache blocks and software simulation. A variable length global table organization is presented which can be used to reduce the size of the global table, regardless of the entry format. Its performance is analyzed using software simulation. A protocol which maintains a linked list of processors which have a particular block cached is presented. Several variations of this protocol induce less interconnection network traffic than traditional protocols

A performance model of multicast communication in wormhole-routed networks on-chip

Collective communication operations form a part of overall traffic in most applications running on platforms employing direct interconnection networks. This paper presents a novel analytical model to compute communication latency of multicast as a widely used collective communication operation. The novelty of the model lies in its ability to predict the latency of the multicast communication in wormhole-routed architectures employing asynchronous multi-port routers scheme. The model is applied to the Quarc NoC and its validity is verified by comparing the model predictions against the results obtained from a discrete-event simulator developed using OMNET++

Exploring emerging technologies for extreme scale HPC architectures

While architectures and programming models have remained relatively stable for almost two decades, new architectural features, such as heterogeneous processing, nonvolatile memory, and optical interconnection networks, will demand that software systems and applications be redesigned so that they expose massive amounts of hierarchical parallelism, carefully orchestrate data movement, and balance concerns over performance, power, and resiliency. This instability has led to two inevitable problems: decreased programmer productivity, and difficult performance prediction. In this talk, I will describe two solutions to these problems, respectively: our OpenARC compiler and runtime system, and our Aspen performance modeling language. First, OpenARC is a research compiler that supports OpenACC and OpenMP4, and can generate code in CUDA, OpenCL, and LLVM IR. OpenARC has enabled us to explore how to enable performance portability of applications across diverse architectures. Second, Aspen is a domain specific language for structured analytical modeling of applications and architectures. It is designed to enable rapid exploration of new algorithm and architectures. Once created, Aspen models can then be used for a variety of purposes including predicting performance of future applications, evaluating system architectures, informing runtime scheduling decisions, and identifying system anomalies